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If an FPGA bank is physically connected to a regulator voltage of 2.5V and in the software the bank is defined as 1.8V and the I/O standard used for the buffers is also 1.8V, the code compiles without errors. Would that work meaning will the I/O pongs be 1.8V standard or will it be based on the bank voltage (2.5V)?

Also just to verify, all the I/O in the bank have to be of the same standard right? I cannot have one GPIO with 2.5V and another with 1.8V.

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    \$\begingroup\$ In the best case, everything may work with 2.5 V outputs and thresholds, but the PAR will be using the incorrect timings. In the worst case, it's not inconceivable that it could program a current that's safe at 1.8 V and damages something at 2.5 V. Use a complex logic system outside its specifications at your own risk. \$\endgroup\$
    – Neil_UK
    Jun 9 at 12:52
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    \$\begingroup\$ It will be based only on the actual bank voltage supply on the board. Software has no role here. But it is your responsibility to convey to the software the correct voltage standard used in the bank. This will aid in PAR for timing and signal integrity. \$\endgroup\$
    – Mitu Raj
    Jun 14 at 4:42

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I'm not sure why you would want to chance it, but I'm sure the answer to the first part is "it depends". For the second question, if you review docs you will see only one IO voltage per bank.

There are vague exceptions in some cases, such as with LVDS. For an example, see

Xilinx 43989

43989

But in general, like the comment by @Neil_UK, at your own risk.

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