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After reading, researching, and asking questions about flip-flops. My understanding is as follows:

  • They are not the only means of storing state but are one of them.
  • The circuit has been constructed in a way that allows it to trap a state, which stays indefinitely while there is current in the circuit until triggered by an external input.

enter image description here In the diagram above, where both S and R are 0, it says to be an invalid or forbidden state. Initially, I assumed it would result in the output that it is unable to change.

Then l constructed a circuit and observed this was not the case, when both outputs (Q and notQ) were the same, I was still able to change the output.

Then I wondered why the emphasis is always on the outputs being the inverse of each other, and why the forbidden/invalid state is discouraged.

I have read a similar question and the answers provided, to me, the answers were still not clear, or did I feel like my question was answered.

I explained that when the outputs are the same with an input trigger the output can still change to a desired output.

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  • \$\begingroup\$ @ElliotAlderson No, it doesn't, it's still not clear \$\endgroup\$
    – Ukpa Uchechi
    Jun 11, 2022 at 11:26
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    \$\begingroup\$ What is it about the answers to the previous question that is unclear? The only difference between your question and the previous question is that the previous question was about a NOR latch rather than a NAND latch. \$\endgroup\$
    – Elliot Alderson
    Jun 11, 2022 at 11:30
  • \$\begingroup\$ it's that I read the answers to the question and I don't still understand why \$\endgroup\$
    – Ukpa Uchechi
    Jun 11, 2022 at 11:33
  • \$\begingroup\$ "In the real world one of the gates will reach the 1 state first and the result will be unpredictable." Please explain how that doesn't answer your question. The latch (this circuit is not flip-flop) is supposed to store a bit (it has 2 stable states), which only happens for the two outputs in opposite levels. If the state after you leave the invalid state is indeterminate, how could this be called storage. \$\endgroup\$
    – devnull
    Jun 11, 2022 at 12:02
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    \$\begingroup\$ Consider that real logic devices have propagation delay and that means a change of state takes time, usually in terms of nanoseconds. With both S & R active (low in this instance) each gate will fight each other and an oscillation occurs. You will need an oscilloscope or fast logic analyser to observe this. Having what you believe is a flip/flop oscillating is not a good thing for correct operation of your logic circuit. I'd suggest you research the term 'metastability' as this is related to this. \$\endgroup\$
    – Kartman
    Jun 11, 2022 at 12:07

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Having S=R=0 causes no smoke. It's called invalid only because you meet difficulties when you try to change S and R both to 1 simultaneously after it. You cannot be sure does Q become 1 or 0. Such uncertainty is not a valid design habit.

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  • \$\begingroup\$ When the both outputs are the same, an input trigger can cause the outputs to change to a desired output. \$\endgroup\$
    – Ukpa Uchechi
    Jun 11, 2022 at 11:52
  • \$\begingroup\$ That's true if there happens to be such property implemented. The circuit in the question is a static one with no clock input. \$\endgroup\$
    – user136077
    Jun 11, 2022 at 14:12

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