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I made and built the following circuit.

enter image description here

It measures current of an AC square wave of roughly ~19 V. The uController calculates a running average of 5 samples every millisecond. If the average exceeds tollerance (which you can set with the potentiometer) the power is cut off for 5 seconds and a red LED will light up. It will automatically re-apply power after 5 seconds.

The square wave is led through the diodes so that both negative and positive cycles flow through the same MOSFET and through the 2 shunt resistors.

The purpose is to split a large circuit which can suffer from physical short circuits into smaller circuits. If one of the circuits suffer from a short, the others remain unaffected (the 5 ms is fast enough). Some loads may draw peak currents of ~1.8 A which are to be ignored. That is what the average calculation is for.

This circuit lacks current limiting. It is designed with AC IN being 3 A or lower. I now have the problem that somebody wants to use this circuit with a 7 A power supply.

I am not sure if my 2 A diodes will survive 7 A for 5 ms. I can alter the software of the prototype to react instantly if more than 3 A is measured in a single sample. And I will increase the sample rate to whatever maximum frequency is possible. I believe I can reduce the short time to 0.1 ms. But I am yet to dive in the attiny's datasheet to see what is achievable.

I figured it may be better to limit the current in the first place. I would like to know how I can incorporate a current limiting circuit of ~1.5 A in my circuit.

(However if a short time of 0.1 ms will protect the 2 A diodes and the MOSFET, that would suffice as well.)

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  • \$\begingroup\$ Get better diodes? \$\endgroup\$
    – winny
    Commented Jun 11, 2022 at 22:11
  • \$\begingroup\$ What diodes, anyway? And is that actually IRF540N or other? \$\endgroup\$ Commented Jun 11, 2022 at 22:20
  • \$\begingroup\$ What frequency is the AC input? \$\endgroup\$ Commented Jun 11, 2022 at 22:23
  • \$\begingroup\$ If the FET is an IRF540 you might not have to do anything, because the sense resistor already steals enough voltage from the Gate to prevent the FET passing more than ~2A. \$\endgroup\$ Commented Jun 11, 2022 at 22:48
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    \$\begingroup\$ Protect your currSense input with a series resistor of some kohm, transient voltage spikes are dangerous for the MCU. \$\endgroup\$
    – Jens
    Commented Jun 11, 2022 at 23:28

3 Answers 3

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You can add a simple current overload detector as shown here:

enter image description here

With the existing two 1 ohm shunt resistors (net 0.5 ohm) the NPN will start to shut off the MOSFET gate when the current through the shunt becomes approximately 0.7V / 0.5 ohm = 1.4A. In practice it will be somewhat higher than that due to the base bias resistor of the NPN transistor.

It is possible to replace the NPN base bias resistor with a pair of resistors (one to GND) acting as a voltage divider to increase the amount of current allowed through the shunt resistors before the shutdown NPN will start to turn on.

You can connect the collector connection of the NPN back to the micro controller to be able to monitor the circuit as a shutdown detection.

Update

I made a simulation of the current detect circuit using LTSpice. I adjusted the component types to parts rated for greater than current and voltage. The circuit below adds the voltage divider to the NPN base to raise the shutdown current level to about 2.1A. I added the C1 capacitor to get rid of some of the switching spikes that make the simulation plots hard to read.

enter image description here

Here is a plot of the current being supplied by the AC input square wave that has 20Vp-p levels at a frequency of 250Hz. As you can see the circuit limits the + and - current levels to 2.1A even when the load fixture has tried to raise the load current to a higher level.

enter image description here

(click on image to enlarge)

This waveform shows the voltage at the current sense node (green) and the voltage of the shutdown detect node.

enter image description here

(click on image to enlarge)

A second NPN transistor can be added to the above circuit in the manner shown here to translate the shutdown/overload detect signal to a full logic swing for a 5V microcontroller.

enter image description here

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You could use your existing shunt 0.5Ω shunt resistance as-is to bias the base-emitter junction of bipolar junction transistor, and pinch off the MOSFET's gate signal when that bias approaches 0.7V.

schematic

simulate this circuit – Schematic created using CircuitLab

Coincidentally, the current required through 0.5Ω to produce 0.7V is:

$$ I_{MAX} = \frac{V}{R} = \frac{0.7V}{0.5\Omega} = 1.4A $$

In practice it's likely to be a little less than that (since \$V_{BE}\$ for a signal transistor is probably slightly less than 0.7V), but you can adjust your sense resistors R1 and R2 to compensate, and modify your microcontroller software to scale the ADC reading accordingly.

Your concerns are possibly moot anyway. As Bruce Abbott appositely pointed out in his comment above, as the voltage across R1/R2 rises, the MOSFET's source potential rises with it, and at some point \$V_{GS}\$ will be insufficient to switch the MOSFET on. You can calculate approximately what current will begin to throttle the MOSFET as follows:

Assume the MOSFET has a gate threshold voltage \$ V_{GS(TH)} = 3.0V \$. The gate is held at +5V w.r.t. ground, as provided by the microcontroller's IO signal. For the MOSFET to turn on, its source must be at least 3V lower than that, at 2.0V. Therefore, if current through the 0.5Ω sense resistor causes it to develop 2.0V or more, the source will rise by that amount, and the MOSFET will switch off without the need for any additional circuitry. The current required to develop 2.0V across 0.5Ω is:

\$ I_{MAX} = \frac{2.0V}{0.5\Omega} = 4A \$

That's more than your desired limit, admittedly, but you should be aware of the possibility of this condition. According to the IRF540 datasheets, \$ 2V \le V_{GS(TH)} \le 4.0V \$, and this uncertainty makes it very difficult to predict exactly what the cut-off current would be, in the absence of any more precise controlling elements.

In theory you could choose a sense resistance that would drop 2V at exactly the current ceiling you desire, and if your MOSFET is truly typical, with \$ V_{GS(TH)} = 3.0V \$, then you don't need to add anything else. However, you lose 2V from input to output, and perhaps that's too much for your application, especially considering you also lose 1.4V across a pair of diodes in the same path, for a total drop of 3.4V.

The addition of Q4 has two beneficial effects:

  1. Reduces the "voltage loss" across the sense resistance to 0.7V at maximum current.

  2. More precisely defines cut-off current.

However, you should be aware that whatever MOSFET you use, it must have \$ V_{GS(TH)} < (V_{ON} - 0.7V) \$ for Q4 to have any worthwhile effect.

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As an alternative approach, I implemented this as a rudimentary discrete analog circuit. The capacitor threshold comparators could be a bit fancier, but they work reasonably as-is.

First, I got rid of the rectifier bridge, and used two mosfets M1+M2 to act as a bidirectional current-limiting switch, set to 1.5A. This limit is always active when the switch is on, and protects the power source and downstream circuitry.

R2 provides the bias to turn the gates on. The remainder of the circuitry can only draw current from R2, and eventually turn the swiitch off.

R1 is a current sense resistor, feeding Q2 and Q4 current sense threshold detectors. When the threshold current of about 1.5A is reached, Q3 or Q5 turns on for positive or negative current respectively, and pulls the gate down to limit the current.

When current limiting is in effect, Q6 is turned on, and R6 triggers the state machine.

D1 rectifies the supply voltage, and R5 is a ballast resistor for a subsequent shunt regulator.

Q1 acts as a gate inhibit switch, controlled from the state machine and the undervoltage lockout.

D6-R19-Q12 form an undervoltage lock-out and a shunt regulator for VCC. When the supply voltage is below about 13V, Q12 is off, and R17 activates the INHibit line via D5. The switch gates are inhibited, and the load is turned off.

schematic

simulate this circuit – Schematic created using CircuitLab

The state machine is implemented around a Set/Reset flip-flop, and the timing capacitor C2.

Q10-Q11 form a Set/Reset flip-flop. C3 ensures that the F/F initializes in the RUN state.

While the current limit gets activated, Q9 turns on and begins to charge C2 via R10. If the current limit persists for about 5ms, the voltage on C2 is high enough to turn on D2, turn off Q10, and switch the flip-flop to the WAIT state.

The WAIT signal turns on the indicator LED D3. It also drives the INHibit line via R16-D4, and turns off the current limiting switch.

After the current limiter turns off, Q9 turns off as well, and C2 starts to discharge via R11. About 5 seconds later, the voltage on C2 is low enough to turn on Q6-Q7, and the flip-flop transitions from the WAIT to the RUN state. The indicator LED extinguishes, the INHibit line goes inactive, and the current limiting switch turns on.

R7-R8-Q7 form a common-base threshold voltage detecting switch for the discharge threshold of C2.

schematic

simulate this circuit

The complete circuit, set up for simulation, is shown below.

schematic

simulate this circuit

Given a low-impedance (1 Ohm) load, the current-limiting action as well as the 5s timeout can be seen on the current plot below.

The current waveform

The voltages at circuit nodes of interest are shown below.

The voltage nodes for the timing capacitor voltage V(CAP), flip-flop outputs V(RUN) and V(WAIT), the RUN trigger V(RUN.SET), the switch gate voltage V(GATE), as well as a 5x magnified inhibit signal V(INH).

The start-up detail of these two plots is shown below:

The start-up detail of the current limiter current The start-up detail of the voltage waveforms

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  • \$\begingroup\$ Most interesting alternative. I won't be using it however. The amount of components is significantly greater. Considering that I am using through-hole components, this design would ultimately cost me more than using a single attiny chip. \$\endgroup\$
    – bask185
    Commented Jun 13, 2022 at 10:48
  • \$\begingroup\$ Of course. An MCU is perfect for this application. I wanted to see how many transistors it’d take to do it without ICs. This design also has a few quirks that would take a couple more transistors to resolve. I tried really hard not to use current sources and mirrors, but they’d definitely improve the accuracy of timing. Differential pairs should ideally be used to detect timing cap thresholds. All in all, a robust analog solution would take twice as many transistors. A bipolar IC for this would be maybe cheaper than attiny if you wanted a couple million of them :) \$\endgroup\$ Commented Jun 13, 2022 at 12:27
  • \$\begingroup\$ I know of an other analog design for a similar device that a toroid was used to distinct a short from a peak load. Essentially that design measured dI/dt and would react only to a short in the order of nano seconds. I hope to achieve the same with a higher sample rate. But not in nano seconds \$\endgroup\$
    – bask185
    Commented Jun 13, 2022 at 13:03
  • \$\begingroup\$ If you achieved nanosecond turn-off, it may damage the load and even the upstream power supply. Wires have about 0.5uH per foot of inductance, 2-4x less if the return wire is in close proximity. Those inductances along with parasitic capacitances will get quite excited by nanosecond pulses. Besides, short circuits work against thermal time constants. Nanosecond turn off will protect semiconductors from overloads order of magnitude higher than the rated current. But for most applications that’s overkill. A fast current limit (here <<1us) with a lazy turn off delay does the trick. \$\endgroup\$ Commented Jun 13, 2022 at 16:45
  • \$\begingroup\$ And an attiny won’t achieve fast enough current limiting. An analog solution is necessary. Then you don’t have the problem of deciding what is a high enough transient to trigger “fast” shutdown: such transients are suppressed by the current limiter. Then it’s just a decision for how long you allow the current limiter to be active continuously before you shut down. The current limiter will of course heat up the mosfets, so the turn-off time must be enough to cool them. But during 5ms they won’t heat up all that much even into a short. \$\endgroup\$ Commented Jun 13, 2022 at 16:49

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