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I have confusion regarding how collector current affects the voltage across collector to emitter in NPN transistor (2N4123). How do I interpret this graph? Can I say when collector current increases voltage Vce also increases in saturation mode?

from Fairchild (Datasheet)

enter image description here

from ON Semiconductor(Datasheet)

enter image description here

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  • \$\begingroup\$ Do the two pictures say the same thing? Why "beta=10" into the first? \$\endgroup\$
    – Antonio51
    Jun 12 at 11:16
  • \$\begingroup\$ @Antonio i have no idea about why beta=10 in first picture.i think minimum hfe for 2N4123 is 25 in datasheet may be related to that.and yes both picture for same transistor 2N4123 but different company datasheet. \$\endgroup\$
    – abulu
    Jun 12 at 12:17
  • \$\begingroup\$ I found a GV paper about Vce sat, but it does not say that there is a mimima in curve versus Ic. I read in deep. Perhaps an explanation? \$\endgroup\$
    – Antonio51
    Jun 12 at 12:35
  • \$\begingroup\$ Pardon me.I just want how collector current affect the Vce.when collector current increase what effect on Vce so I relate these things to sinking capability of transister.. \$\endgroup\$
    – abulu
    Jun 12 at 12:42
  • 1
    \$\begingroup\$ Generally, Vcesat grows with Ic ... Don't understand the first picture ... until knowing how it is obtained. \$\endgroup\$
    – Antonio51
    Jun 12 at 12:49

4 Answers 4

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As I was surprised by a picture as the first of OP, I tried to find it by simulation.
No too easy, as we "do not know" how it was obtained and what is the signification of beta=10.
I guess that beta=10 is the "forced" beta, that is to say, that the imposed currents would be so that \$Ic=10*Ib\$.

And here is what the simulation says (not too bad ...).

enter image description here

As generally, Ic currents are "large", we use the assumption that Vce_sat grows with Ic, it is obviously the case ... except for very low "Ic" (perhaps useful and used in integrated circuits).

NB: Note that the second OP picture does not say the "same thing" because Ic current is not "interpolated" between 1 and 10 mA, thus this "conclusion" can't be checked ...

from this paper ... June 1977
NBSIR 77-1231 ~ Measurement of Transistor Collector- Emitter Saturation Voltage

enter image description here

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  • \$\begingroup\$ To be more exact: There is no "injected current". The definition of saturation is as follows: When the voltage drop across the coll.resistance is so large that Vc falls below Vb , also the B-C junction now is forward biased and the base current now consists of two parts and increases drastically - and the hfe is meaningless. Hence, the large base current is the RESULT of saturation (and not its cause)! \$\endgroup\$
    – LvW
    Jun 13 at 7:47
  • \$\begingroup\$ Ok. It is not the right "word"... It would be "forced", or "imposed" by an external source of current. I change it. \$\endgroup\$
    – Antonio51
    Jun 13 at 8:42
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Interesting question. I try my 2 cents on the matter, it's just a guess, don't take me seriously.

In a BJT, saturation voltage \$V_{CE}\$ depends on many factors, the two most important being the voltage difference between the two forward biased junctions (\$V_{BE}-V_{BC}\$) and the voltage drop across the parasitic resistances, specially the collector one.

In your case collector current is minuscule, so probably the collector parasitic resistance is not important.

Voltage difference between BE and BC can be derived from Ebers-Moll or transport equations and the result is (Millman Grabel - Microelectronics)

$$ V_{CE_\text{sat}}=V_T\ln \left(\frac{\frac{1}{\alpha_R}+\frac{\beta_\text{for}}{\beta_R}}{1-\frac{\beta_\text{for}}{\beta_F}}\right ) $$

where \$\beta_\text{for}\$ is the forced beta, that is the ratio between collector current determined by the load and base current injected into the base (in your data sheet it's 10). \$\beta_F\$ and \$\beta_R\$ are the forward and reverse current gains. \$\alpha_R=\frac{\beta_R}{\beta_R+1}\$ is the reverse base transport factor.

Betas aren't fixed numbers for a transistor, carved in stone, they vary with current, temperature, collector voltage, moon phase... (see for an in dept analysis of beta changes: Gray Meyer - Analysis and Design of Analog Integrated Circuits)

I suspect that in this case when the tiny \$I_C\$ increases, \$\beta_F\$ increases as well (in theory it should be proportional to \$\sqrt{I_C}\$), the logarithm argument decreases and \$ V_{CE_\text{sat}}\$ decreases. Unfortunately I have no news about the behavior of \$\beta_R\$ :(

A final general warning about data sheets, not really applying to this case. "Static parameters", like saturation voltage, beta..., are measured with a pulsed technique to avoid heating the silicon. Unfortunately at very low current there is no time to charge or discharge the parasitic capacitances and in some cases this effect is even visible on data sheets.

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Almost :)

The C-E voltage is lowest at the collector current around 5mA. It increases whether you decrease or increase the current away from this saddle point.

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Can I say when collector current increases voltage Vce also increases in saturation mode?

Yes, you can - assuming no other variables are changed. However you might be a little confused by the datasheet graphs because they do not show this relationship directly.

The first graph shows Collector voltage when Ib is forced to Ic / 10. At this point the transistor is well into 'hard' saturation, where changes in Base current have little effect on Collector current. A ratio of 1:10 is commonly used as an 'overkill' to guarantee saturation independent of the individual device's 'normal' current gain.

The second graph shows how increasing Base current reduces Collector voltage at different fixed Collector currents. This is useful for determining how much Base current current you should apply to ensure that the transistor saturates when switching a particular Collector current.

To see the direct effect of Collector current on Collector voltage with fixed Base bias, you need a different graph. I generated the graph below using LTspice to simulate a 2N4124 with a fixed Base current of 100 uA:-

enter image description here

Here we see that - as expected - Collector voltage always increases as Collector current increases. In this example the transistor comes out of hard saturation above ~20 mA. Technically it is still in saturation until Collector voltage reaches Base voltage at 0.75 V, but above ~0.3 V it is in the 'soft saturation' region where it is acting almost the same as at higher Collector voltages.

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