Syntax error in continuous assignment

Question

Why is there a syntax error in the continuous assignment to the out_money signal?

module tb;
  reg clk, reset_b, start;
  wire [15:0] seed, q, random;
  wire        seed_pulse;
  reg [6:0] in_money ;
  reg [3:0] in_value1, in_value2, in_value3 ;
  reg [10:0] out_money;
     
  counter u1(.clk(clk), .reset_b(reset_b), .start(start), .cnt(seed), .seed_pulse(seed_pulse));
  lfsr u2(.clk(clk), .reset_b(reset_b), .seed_pulse(seed_pulse), .cnt(seed), .q(q));
  random u3 (.clk(clk), .reset_b(reset_b), .start(start), .q(q), .random(random));
     
  initial begin
    in_value1 = 4'd3;
    in_value2 = 4'd0;
    in_value3 = 4'd0;
  end
    
  wire [3:0] random1, random2, random3;
    
  assign random1 = random[11:8]%10;
  assign random2 = random[7:4]%10;
  assign random3 = random[3:0]%10;
  assign out_money = ((random1 == in_value1) && (random2 == in_value2) && (random3 == in_value3)) ? in_money * 10 ;
    
  initial clk = 0;

  always #5 clk = ~clk;

  initial begin
    reset_b = 0;
    #8 reset_b = 1;
  end
     
  initial begin
    start = 0;
    #38 start = 1;
    #100 start = 0;
    #50 $finish;
  end
     
  initial
    $monitor("time:%3d, start:%b, seed: %d, lfsr: %d, random: %d", $time, start, seed, q, random);
     
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
  end

endmodule

Answer 1

Some simulators do not yield very descriptive error messages. But, others sometimes do. You can try to compile your code on multiple simulators available on the edaplayground site.

The Cadence simulator shows:

  assign out_money = ((random1 == in_value1) && (random2 == in_value2) && (random3 == in_value3)) ? in_money * 10 ;
                                                                                                                  |
xmvlog: *E,BADTNO : expecting a colon (':') in the conditional operator [4.1.13(IEEE)].

This informs you that the compiler thinks you are trying to use the conditional operator, which has the general form:

(condition) ? expression1 : expression2;

You code has the "condition" and "expression1" components, but it is missing the colon and "expression2".

To get rid of the syntax error, add a "expression2". For example:

  assign out_money = ((random1 == in_value1) && (random2 == in_value2) && (random3 == in_value3)) ? in_money * 10 : {10{1'b0}};