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As im learning about Computer Architecture im trying to understand it from the ground up (Transistors in CMOS in particular)

I came across the simple 6T schematic for SRAM (2 inverters) 6T Array

Mostly makes sense, but I have a few questions. What exactly is being done with whatever is stored here? Is it being sent to the CPU? a Decoder?....etc...? I'd assume we use some sort of decoder/encoder to write to specific cells?

And while I understand how the Memory Cell works (Keeps it's data from feedback) are we reading the Cells contents with the Word lines or Bit Lines? what about writing to them? Is the ~Bit Line (~BL) completely useless to us?

Like how would I go about reading and writing to an array like this?

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  • \$\begingroup\$ What is the actual component? \$\endgroup\$ – Leon Heller Mar 25 '13 at 20:24
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The memory is addressed using the word lines, and data is transferred into or out of the array using the bit lines.

The word lines are driven from a decoder whose input is the address bus. For any particular binary address, exactly one word line is activated. This turns on all of the pass transistors for one complete row of memory cells, connecting each pair of cross-connected inverters to its pair of bit lines. All of the other rows in the memory array are disconnected from the bit lines and do not participate in the read or write cycle.

When reading a cell, the inverters drive the bit lines — one high and one low — and circuitry not shown compares the voltages on the two bit lines and decides whether the bit is a zero or a one. The bits obtained in this way are grouped together to form a "word" of data, which is then passed to whatever external logic (CPU, video controller, or anything else) that might be connected to the data bus.

When writing a cell, another set of circuitry, also not shown, drives the bit lines — again, one high and one low for each cell. The key here is that the write driver is stronger than the inverters in the memory cell, and can impose a new state on the memory cell regardless of what its previous state might have been.

At the end of the cycle, the word line is deactivated and the cells retain their state.

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  • \$\begingroup\$ Im assuming those transistors on the WL are N-Channel Mosfets? and what are these "comparative circuitry" that compares the voltages? Where are they located? (I've found tons of memory array pictures, but not much explanation :( ) \$\endgroup\$ – user3073 Mar 26 '13 at 12:23
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    \$\begingroup\$ 1) Yes, probably N-channel, for better speed. 2) The voltage comparator is a differential amplifier. 3) A row of these, one per column, is typically located along the top or bottom edge of the memory cell array. The drivers for writing will be located along the opposite edge. The word line drivers (the last stage of the address decoder) are located along the left and/or right edges of the array (sometimes both). \$\endgroup\$ – Dave Tweed Mar 26 '13 at 14:04
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To write to a one or more cells on a single SRAM row, one should strongly drive both the inverted and non-inverted bit-lines for the appropriate columns with complementary values, float all the other columns, and then drive the appropriate row-select wire high. Columns which are strongly driven externally will hold the states forced by those external drivers, while others will accommodate themselves to the states stored in the memory cells on the selected row. All memory cells on the selected row will latch the data on their appropriate columns, which will either be the externally-driven data (for the driven rows), or the data the memory cells already contained (for the non-driven ones).

To read one or more cells, float all the columns and drive the appropriate row-select wire high. All columns will then accommodate themselves to the states of the appropriate memory cells. When reading, one could use one bit line from each column and ignore the other, or one could feed both lines into a voltage-comparator circuit. Even though the latter approach would require more circuitry, it could offer better performance since the comparator's output could switch before the column wires had achieved valid logic levels.

It's worthwhile to note that if one uses two select wires for each row, one of which operates the left-side transistor in each column and one of which operates the right side, one may fairly easily implement a memory which can accommodate either two simultaneous reads or else one write (reliable writing will in many cases require driving both wires associated with a column, but reading only requires one).

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