I'm currently learning about transistor amplifiers. I've designed this CE amplifier circuit that should yield an ac voltage gain close to 100.

enter image description here

I assume my calculations where right, as it seems to work when I simulate it using NI Multisim: I'm giving it an input of 10mV peak and I'm getting approximately 1V peak at the output.

enter image description here

When I built the circuit on a breadboard and measured the output with an oscilloscope, I got 3V peak at the output instead of 1V peak, which means a gain of 300. I used the same parameters as in the simulation for the input: 10KHz, 10mV peak sine from a function generator.

I used a BC337-40 NPN transistor. The trimpot at the input is used as a voltage divider to get the 10mV peak from the function generator.

enter image description here

enter image description here

I eventually managed to fix this by adjusting R2 to 12.5K, but it doesn't make any sense to me why it works with this value.

Why is the circuit providing the right voltage gain in the simulation but not in reality?

I'm also not sure why the output isn't symmetrical. I think it's caused by the bypass capacitor (C3) but I'm not sure. Is it possible to correct that?

Calculations :

All of my calculations are based on the book "All New Electronics Self Teaching Guide, 3rd ed." (Harry Kybett & Earl Boysen), Chapter 8 : "Transistor amplifiers" (see pages 257 and 263).

It's a book for beginner so I think it might be oversimplifying certain steps. For instance : it doesn't explain how to define the Q-point, which could explain the lack of accuracy. However, I still expected to get a coherent result with the circuit...

Here's how I found the values used in the circuit :

  1. Defined :

    Vs = 12V
    Vc = Vs/2 = 6V
    Av = 100
    ß = ~205 (Measured at room temperature with a multimeter)

  2. Calculated resistor values :

    Rc (R3) = Vc/1mA = 6/0.001 = 6k
    Re (R4) = Rc/Av = 6k/100 = 60 Ω
    Ve = (Vs - Vc)/Av = 6/100 = 60 mV
    Vb = Ve + 700 mV = 760 mV
    Ic = (Vs - Vc)/Rc = 6/6k 1 mA
    Ib = Ic/ß = 1 mA/205 = ~4.9 µA
    I2 = 10*Ib = 10 * 4.9µA = ~49 µA
    R2 = Vb/I2 = 760 mV/49 µA = ~15.5k --> 16k
    R1 = (Vs - Vb)/I2 + Ib = 11.24/53.9 µA = ~208.5k --> 220k

  3. Calculated bypass capacitor value :

    Fl (lowest input frequency) = 20 Hz
    Xc = Re/10 = 5.7 Ω
    Ce = 1/(2πXcFl) = 1/(2π5.720) = ~1 400µF (--> 1 000µ + 470 µF in parallel)

  • 2
    \$\begingroup\$ Show us how you calculated the component values for a gain of 100, why you chose the particular bias point you did, and what assumptions you made about the transistor's parameters. \$\endgroup\$
    – user16324
    Commented Jun 17, 2022 at 12:34

7 Answers 7


Let's start with some simple calculations based only upon a few starting points:

  • \$R_{_\text{C}}=6\:\text{k}\Omega\$
  • \$A_v=100\$
  • \$V_{_\text{CC}}=12\:\text{V}\$
  • \$v_{_\text{PP(IN)}}=20\:\text{mV}\$

All of the above are taken from your schematic.

It's easy to compute \$v_{_\text{PP(OUT)}}=20\:\text{mV}\cdot A_v=2\:\text{V}\$. In addition, \$V_{\text{CE}_{_\text{MIN}}}=1\:\text{V}\$ in order to avoid saturation. So at best you only have about \$9\:\text{V}\$ left over. Let's assign most of that to \$R_{_\text{C}}\$ such that \$R_{_\text{C}}\cdot I_{_{\text{C}_Q}} = 8\:\text{V}\$ or that \$I_{_{\text{C}_Q}}=1.\overline{3}\:\text{mA}\$. But ignoring \$r_e^{\:'}\approx 20\:\Omega\$ for now, this means that with \$R_{_\text{E}}=60\:\Omega\$ we find \$V_{_{\text{E}_Q}}=80\:\text{mV}\$!

There is no possible way to design for that, assuming real parts that you can grab out of a bag. Even a \$50\:\text{mV}\$ difference between one BJT and another would mean more than a 50% shift in the quiescent operating point! And a 50% shift in the wrong direction means that \$R_{_\text{C}}\cdot I_{_{\text{C}_Q}} = 12\:\text{V}\$ instead and there's no room left over for anything else. The entire power supply is gobbled up. And things are likely to be much worse.

And I haven't even gotten to \$r_e^{\:'}\$'s impact on the voltage gain -- which is substantial -- or the fact that ambient temperatures from one place to another in the world can vary widely enough to completely ruin the design, even assuming every single BJT from a bag were identical (which they are not.)

For any chance at all in just getting parts out of a bag and having a circuit operate reasonably similarly over both variations in ambient temperature and also variations in BJT parts, you will need \$V_{_{\text{E}_Q}}\ge 500\:\text{mV}\$ (and likely still more than that to be safer.) But this means that \$R_{_\text{C}}\cdot I_{_{\text{C}_Q}}\ge 50\:\text{V}\$!!! So we are looking at a very large power supply rail and a BJT that can stand off that voltage, too! (2N5551?) We are already now starting to think in terms of \$I_{_{\text{C}_Q}} \approx 10\:\text{mA}\$, too! The only nice thing about all this is that \$r_e^{\:'}\approx 2.5\:\Omega\$ now and that means that \$R_{_\text{E}}\approx 56\:\Omega\$ could work here.

Let's do that design and see where it goes. New specs are:

  • \$A_v=100\$
  • \$R_{_\text{C}}=6\:\text{k}\Omega\$
  • \$R_{_\text{E}}=56\:\Omega\$
  • \$I_{_{\text{C}_Q}} = 10\:\text{mA}\$
  • \$V_{\text{CE}_{_\text{MIN}}}\ge 4\:\text{V}\$
  • \$v_{_\text{PP(IN)}}=20\:\text{mV}\$
  • \$v_{_\text{PP(OUT)}}=2\:\text{V}\$
  • \$T_{_\text{MAX}}=55^\circ\text{C}\$ and \$T_{_\text{MIN}}=-20^\circ\text{C}\$,

From this, I find \$V_{_\text{CC}}\ge 65\:\text{V}\$ to be good enough. I'll use a 2N5550 BJT for this, as it has sufficient \$V_{_\text{CEO}}\$.

I don't know the \$\beta\$ of any given part, but the above datasheet says that when \$I_{_{\text{C}_Q}} = 10\:\text{mA}\$ then \$\beta_{_\text{MIN}}=60\$. So that means we design for that base current. Also, I think that we should use, based upon the charts in that datasheet and considering the temperature range at hand, that \$V_{_{\text{BE}_Q}}\approx 750\:\text{mV}\$.

We can find that \$V_{_{\text{E}_Q}}=56\:\Omega\cdot 10\:\text{mA}\cdot\frac{1+\beta=60}{\beta=60}\approx 570\:\text{mV}\$ and that \$V_{_{\text{C}_Q}}=65\:\text{V}-6\:\text{k}\Omega\cdot 10\:\text{mA}= 5\:\text{V}\$.

\$R_1\$ and \$R_2\$ should be rated to pass \$10\times\$ the base current for a stiff biasing pair. So \$R_2=\frac{570\:\text{mV}+750\:\text{mV}}{10\cdot\frac{10\:\text{mA}}{\beta=60}}= 864\:\Omega\$ and \$R_1=\frac{65\:\text{V}-\left(570\:\text{mV}+750\:\text{mV}\right)}{\left(10+1\right)\cdot\frac{10\:\text{mA}}{\beta=60}}\approx 34.73\:\text{k}\Omega\$.

Dropping down to a standard value I'd get \$R_2=820\:\Omega\$ and given that I expect \$\beta\$ to be a bit better than the absolute minimum I'd choose to round upwards so that \$R_1=39\:\text{k}\Omega\$.

We are still cutting things thin because \$V_{_{\text{E}_Q}}\approx 570\:\text{mV}\$ and this still isn't really a good enough margin (I'd like at least twice this much and actually more like four or five times more.) But at least we've a chance in the design.

Let's see what LTspice says:

enter image description here

Okay. I consider that a good result. I still feel this is a bit dicey. And I'd still expect some trouble if I were to put this onto a protoboard. (I've not accounted for bulk impedances for the 2N5550 at the emitter, for example, and I don't have the voltage margins I'd like at the quiescent emitter. But at least I feel I'd have a shot at it.)

As you can see, the voltage gain is very close to what's desired, too!

But I think you can now see that trying to get \$A_v=100\$ in a single BJT stage is 'difficult,' at best.

I haven't yet talked about THD and distortion or the use of global NFB. These are whole other topics. But I think the point remains. With only \$12\:\text{V}\$ to work with and only a single BJT stage to work with, high voltage gain isn't in the cards.

  • \$\begingroup\$ The reason I went for a voltage gain of 100 is that the book I'm using to study says that without a bypass cap you can get a max gain of 50, but if you add one, you can obtain a higher gain. That's what it precisely states : "You can make an amplifier with stable bias points without giving up high AC voltage gain by placing a capacitor in parallel with the emitter resistor." It didn't mention the maximum possible gain though... \$\endgroup\$
    – Matthew_R
    Commented Jun 20, 2022 at 14:00
  • \$\begingroup\$ @CyberElectronics I intentionally neglected "seeing" your bypass capacitor for a reason. To paint the biasing problem, which also applies for any design (including one with a bypass capacitor) that attempts to achieve a fixed voltage gain. With a bypass capacitor, the only way you get a fixed DC gain is to place a resistor in series with the capacitor. And as soon as you do that, you have the above problem, again. A bypass cap yields a variable gain that varies as signal varies. This effectively means distortion. And that means you need global NFB somewhere else to fix it. \$\endgroup\$
    – jonk
    Commented Jun 20, 2022 at 16:29

It seems to me that with an emitter resistor of 60 Ω and a collector resistor of 6 kΩ you should get reasonably close to a gain of 100 without the 1470 μF emitter capacitor (C3). It's most likely that its very low impedance (at circa 10 kHz) is causing this to happen.

I'm also not sure why the output isn't symmetrical, I think it's caused by the bypass capacitor (C3) but I'm not sure. Is it possible to correct that ?

C3 shouldn't be needed here and I always discourage folk from using an emitter capacitor that is directly across the emitter resistor because of the unknown impedance it presents and the highly non-linear artefacts it creates.

  • \$\begingroup\$ The output does in fact look better without the capacitors and it drops from 3V peak to 0.85V, which is way closer to the desired voltage gain. It works even at 20Hz, so I'm not sure I understand the purpose of this bypass cap... \$\endgroup\$
    – Matthew_R
    Commented Jun 20, 2022 at 14:16
  • \$\begingroup\$ The bypass capacitor (without a series resistor) appears to have been invented by people not understanding what they are trying to do \$\endgroup\$
    – Andy aka
    Commented Jun 20, 2022 at 14:25

R2/R1 set the base of the transistor at about 0.81V above ground. This means there should be about 0.2V across R4, which means ~ 3mA collector current. So the 6k collector resistor would have 18V across it, which isn't possible, and the transistor would be saturated. So, something's wrong with the values.

If you adjust R2/R1 to have, say, 5V across R3 for good headroom on both sides, then the voltage across R4 will be tiny, about 0.1V. You can try to do this and measure it.

Next, while measuring voltage across R3, blow on the transistor then put your finger on it to heat it. You should observe large variations on the measured voltage.

The Vbe of a bipolar transistor has a tempco of about 2mV/°C, and there is some dispersion between any two transistors from the same series. Therefore the voltage across R4 should be larger (so R4 should be higher) so that these variations do not represent a significant part of this voltage.

In addition, the gain of the circuit is determined by the transconductance of the transistor, and the impedance of C3. There is no resistance in series with C3, so that'll be its ESR and impedance at the frequency of interest. BJT transconductance is proportional to emitter current, so your gain will be proportional to emitter current, which is going to vary quite a lot depending on the temperature of the transistor.

So it's not surprising that you don't get the same results as in simulation, because in simulation, all transistors are the same and they don't heat! So it is easy to adjust the voltage across R4 to an unrealistic low value. But it doesn't work in reality.

  • \$\begingroup\$ Ok that means something is obviously wrong with my resistor values, but I'm not sure where I did a mistake. I adjusted the voltage across R3 to be 5V and measured about 50mV across R4. I did observe up to a 50mV variation of voltage across R3 while cooling and then heating the transistor. Idk why I obtained such a low value for R4, but it seems like the method I used to find out the resistor values is not right... \$\endgroup\$
    – Matthew_R
    Commented Jun 20, 2022 at 18:23

Simply use the simulation probe or real scope probe at the transistor's collector to see its average DC voltage.

The top of the waveform is squashed with distortion which is normal at high output levels with no negative feedback. C3 is preventing negative feedback.

The hFE of each transistor is different. Your real BC337-40 transistor has a high hFE typically 400 but the unknown transistor in the simulation might have an hFE of 100 or less.

Then the simulation transistor is near cutoff with its collector voltage near 12VDC. The top pf its waveform will be VERY squashed. The BC337-40 will have its collector voltage fairly low with only a little amount of squashing and a higher output level.

Negative feedback will give accuracy. squashed


For stable dc biasing it is typical to aim for at least 1 volt at the transistor's emitter. The larger the dc bias at the transistor's emitter then the smaller will be the dc emitter current changes due to temperature variations (Vbe variations). Less variation in dc emitter current due to temperature variations results in less variation of the collector dc bias. Also, making the dc emitter voltage equal to at least 1 V will reduce dc emitter current variations due to changes in beta caused by, for example, using a different transistor in the amplifier. Beware of making the dc emitter bias voltage too large as this can limit available output signal amplitude.

With your value for R2=16k there is only a very small dc bias voltage at the emitter and with R2=12.5k there is virtually no dc bias voltage at the emitter. This is not good design.

So, to get about 1 V dc bias at the emitter you need to increase the value of R2 to 39k to set the base dc bias to about 1.7 V giving Ve=Vb-0.7V = 1V. A typical value for emitter current would be around 1 mA and therefore R4 is set to 1k (1V/1mA=1k).

With a 1mA emitter current the collector current will also be about 1mA and so setting R3 to 6.2k biases the collector to about mid-supply voltage for near maximum signal swing in either direction.

re, the intrinsic emitter resistance is equal to VT/Ie = 25mV/1mA = 25R and with a completely bypassed emitter resister the gain would be 6k2/25 = 248, too high as you only want a gain of 100. One way to reduce the gain down to 100 from 248 is to add some resistance in series with the emitter bypass capacitor.

A value of 36R for R5, the series resistor, nicely brings the gain down to about 100.

The value for the gain = R3/(re + R4//R5) = 6k2/ (25 + 1k//36R) = 103 which is pretty close to what the Circuit Wizzard simulation below shows.

The 1M load resistor is so high in value that it will hardly affect the circuit's gain but you would find that if you were to reduce the load resistance it would have the effect of loading the amplifier more with a resulting reduction in gain.

Transistor amp


It is not clear to me what C3 is supposed to do in your circuit. R4 and C3 combined have a corner frequency of about 2Hz, meaning that for frequencies higher than 2Hz, R4 is getting bypassed and your circuit becomes essentially a differentiator (if you can get your scope to show both input and output, the phase shift should be obvious) with an amplitude that is related to the gain factor of the transistor.

Bypass capacitors are usually employed when there is separate negative feedback other than the emitter resistor: the emitter resistor in circuits with bypass capacitor is for stabilising the DC operating point. A typical point you'll find it in is tone controls that will use a bridge circuit (which can be unbalanced at several operating frequencies with pots) that tries to regulate the center point to 0V by using the full AC gain of the transistor for generating the mirror point of the bridge as output.

In that case, you want maximum AC gain while stabilising the DC operating point. Hence, the bypass capacitor.

But if you have a bypass capacitor, you need some negative feedback other than the emitter resistor for AC signals.


By using C3 without additional resistor in series, you are using the BE impedance as emitter resistor in it's normal operational frequency, which is forming the voltage gain of

g = R3 / R_BE

Internal BE impedance is not a resistor, rather, a BE diode that depends upon current, voltage, and temperature among other things. Usually it is assumed roughly around 50 ohms, but it's not to be relied upon, and commonly used inside a negative feedback amplification with a much less closed loop amplification

Your experiment with this maximum open loop gain is very good to obtain the actual information i.e. the maximum open loop gain, and now you can use resistor in series with C3 to get a more stable amplification of say 10x, by using:

6k ohms / 10x = 600 ohms.

A closed loop amplifier is preferable by using a feed back resistor from collector to base, with closed loop gain of 30x or less, where the distortion are suppressed by around 300x / 30x or maximum of 10% distortion


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.