# Phase Shifted Full bridge converter transformer design

I am designing a transformer for a phase shifted full bridge converter for voltage up conversion. My main concern is the efficiency, I am trying to reduce transformer loss to less than 5%. The total power is 1000W. First I was using LLC topology, however since it adds another constraint of leakage inductance, I found it hard to design and moved on to PSFB.(I am new to all of this and if LLC is still easier please guide me)

fs = 100kHz

Vin min = 36V

Vin max = 60V

Vin nominal = 48V

Vout = 400V

I used the Vin min for the design since the current is at maximum then.

So far I have bought this Ferrite core and bobbin.
Ferrite core
Bobbin

I chose this EER49 core by going through TDK catalog and referring to recommended power capabilities of the cores. However at the time of purchase the TDK cores were out of stock and I had to go with Fair - Rite brand. The properties of the material "98" is listed in this website under "Power Materials", I guessed the Flux Density row refers to the Bmax of the material. For the material 98, it is listed as 500mT. I am planning to use many strands of AWG 28 magnet wire in the primary, I referred to this chart for selecting magnet wire.

First I followed a guide from Texas Instruments.

https://training.ti.com/transformer-designer-isolated-high-voltage-power-design

There he introduces equations for each constraint in the design process.

First equation is the primary inductance equation.

$$L_{pri} = \frac{n^2 A_e \mu_0}{l_g}$$

$$\A_e\$$ = effective cross section of the core $$\245mm^2\$$

$$\\mu_0\$$ = permeability of free space

$$\l_g\$$ = air gap length

The air gap length was taken as $$\10\mu m\$$, after referring to this website. I used the value listed as Normally ground, the core itself does not have a purposely made air gap.

The second constraint is to avoid saturation.

$$n I_{max} = B_{max}\frac{l_g}{\mu_0}$$

As I understood the $$\n I_{max} \$$ should not exceed the RHS. I do not know what to exactly put as the $$\I_{max}\$$ here. If I choose the DC equivalent for 1000W at 36V I get 27.78A, so even at 1 turn I simply exceed the RHS and saturate the transformer.

I also referred to this thread.

How to calculate air gap in flyback transformer?

However it discusses about a flyback transformer, after going through PSFB converter theory I understood that the input voltage square waveform can be approximated to its first harmonic in PSFB.

I am stuck right now. What should be the proper $$\I_{max}\$$ value?
Should I purposely make an air gap such that the RHS becomes bigger? I am hand crafting this transformer, is it possible for me to keep the air gap close to $$\10 \mu m \$$?
Are the steps I have taken correct at all?
I read that toroidal cores offer low losses in the transformer, should I use a toroidal core? If so what should be the equations?

• FYI, there is a minimum equivalent air gap, l_e / mu_r. This is the length of air gap corresponding to the core's reluctance; mu_r is simply saying that the core is effectively so-many times shorter than it physically is. Replacing l_g in the above equation with (l_g + l_e/mu_r) does the trick. Jun 19, 2022 at 7:32
• No gaping! You want high magnetizing inductance. Jun 19, 2022 at 8:32

Don't concern about the magnetizing current. Those formulas are for inductors (coupled as the case may be for flyback). Transformers for forward converters use high inductance, maybe a thin air gap to increase free ringdown frequency a little bit (can have implications for coupling capacitor, rise/fall edge symmetry, flux walking).

(Does your control have a means to balance flux, or do you have a coupling capacitor in series with the inverter and primary? If not, consider making such a change.)

Typical transformer design is:

• Determine acceptable peak flux density Bmax. This is usually driven by core loss, with ~200mW/cm^3 being a typical figure for larger cores. Exact figure depends on acceptable efficiency, or temp rise and ventilation, etc.
• Calculate primary turns: $$\N = \frac{V}{4 F B_{max} A_e}\$$. V is peak voltage (square wave), F is frequency, Ae is core effective area or cross section.
• Calculate secondary turns: just the voltage ratio. Note this is at minimum Vin and maximum Vout (at full 180° phase shift), plus some margin if you want to maintain regulation under that condition, and to account for strays (switch/diode losses, leakage).
• Determine interleaving from required impedance or leakage.

For reference, a pair of single-layer windings (primary and secondary single layer each) approximates the geometry of a twin-lead transmission line, so has similar inductance per length, and has a characteristic impedance around 100 ohms. This works when the turns ratio is low (near 1:1).

The impedance can be considered with respect to each winding. For example if a winding is switching 320V 5A, that's 64 ohms, not a terrible mismatch, so one layer pair would suffice. If it were say 48V 30A, that's 1.6 ohms and leakage will be considerable; many layers, interleaved, and wired in parallel, will be necessary (more than 4?).

Note one advantage of PSPWM, it's very tolerant of leakage: the reactive energy is recycled by the full bridge -- so it's much less of an issue in this case.

This is also where you can introduce leakage intentionally, if necessary (as for LLC types). Usually by winding in banks, maximizing distance (minimizing interleaving) between them. For the record, for a novice LLC design, I would recommend using a transformer with good coupling, in series with a separate external inductor for "leakage" -- it's easier to work with, as you've perhaps already realized. The design can always be optimized later.

In this case, with 48V primary and 400V secondary, you will want multiple full-width layers of primary. Between which, the secondary layers can be placed, all wired in series.

Or maybe you do the secondary layers in parallel, perhaps you find it easier to use thinner wire per layer, and parallel them up afterwards -- it doesn't make any difference, the leakage is the same because you've use N times more wire length per layer, dividing by N in parallel. You have the same total length for a series arrangement.

The same is true for the primary of course, but you likely won't be needing enough turns to have anything to wire in series, so parallel is the only option. The properties work out the same, series or parallel, but you may have numerical restrictions like this that prevent one or the other.

• Determine wire size and type.

At this frequency and power level, likely you want either foil, or some kind of stranded -- braid or litz cable -- for the primary. The secondary, probably a few strands in parallel would do, or litz. The fields between wires are quite complex, i.e. there's a lot of eddy currents here, likely you can make up a lot of efficiency points here by using finer stranded materials and relatively a lot of them. This will be more expensive of course -- quite literally the price of success, as far as high efficiency goes.

• Any other considerations: shielding, isolation voltage, etc.

You likely want shielding for PSPWM: note that, even at 0% PWM output, there is 100% full amplitude square wave applied to the primary, with respect to inverter ground. This couples directly through the transformer capacitance -- which will be relatively high due to interleaving* -- and across the isolation barrier. 48Vpp will not only violate every EMC standard there is (heh, well, all that I know of at least), but is likely to cause functional problems within the circuit already.

(This is a big point in favor of LLC, as the series inductance acts to soften the sharp edges from the inverter. The inverter phases can also be complementary, reducing CM noise to the small timing difference between phases: that is, it can operate at 180° PSPWM all the time.)

*Which, again, you have some tolerance for with PSPWM, so this might be another point in favor of less interleaving. So like, 4 layers instead of 10+?

Shielding modifies the leakage situation. Consider the geometry of a single layer of wire, then insulating tape, shield foil, more tape, and another single layer of wire. This resembles a pair of round-wire-over-ground-plane transmission lines. The impedance of which is a bit lower than for twin lead (round wire pair, no ground), but both act in series with the shield in the middle, so the overall result is a somewhat higher impedance.

Shielding also increases losses somewhat, as the shield itself blocks the nonuniform magnetic fields around individual turns. It should be very conductive (copper is better than aluminum, and air on the thick side, i.e. several skin depths), so that fields are mostly reflected rather than absorbed (but there will always be a small difference which is absorbed, and thus, losses).

The shields shall be foil, single turn layer, full width. The purpose is to make a cylindrical shield between layers, not a full contiguous cylinder, but a slitted cylinder so that it doesn't act as a shorted turn overall. (Leave the ends overlapping slightly, to ensure no field leaks through the slit; make sure the lapped ends are insulated with tape to prevent shorting!) Make connection to the midpoint (half turn, as it were) and tie all shields off to one or more pins (use up any spare pins on the bobbin, maybe?), and then to primary common.

This then reduces the common mode situation to a voltage source of, whatever field sneaks around the shields, or across the transformer itself (winding terminations, etc.?), and whatever drops across the shields (primary capacitance to shield, shield impedance to primary GND -- keep lead length short to minimize stray inductance). You'll still have, probably a couple volts peak, and it will be only spiky, ringing stuff -- much easier to filter. (Output CMC should be on the output side, as current is least there.)

• Putting it all together:

Say Bmax is 200mT, then: $$N_p = \frac{(48\,\textrm{V})}{4 (200\,\textrm{mT}) (100\,\textrm{kHz}) (2.45\,\textrm{cm}^2)}$$ About 2.5 turns. Choose 3. This must carry over 20A, but is shared between 4 (or more?) layers, so each individual layer doesn't need to be too much. Choose foil, around 10mm width, 0.1mm or so thickness should do. Measure and cut to required dimensions width and length, then wrap each strip with tape, then wind on the bobbin. Termination can be solid or stranded wire back to the pin(s), that's not a big deal (and a lot easier than wrestling foil out of there).

Layer stackup shall be PsSsPsSsPsSsP, i.e. 4 Primary, 3 Secondary, 6 shield, all interleaved. Pri-shield insulation doesn't need to be much, but shield-sec insulation needs to meet isolation requirement.

Secondary must carry over 2.5A, probably 7 or 19 stranded, 22AWG-equivalent litz will do. >= 25 turns is required. Hmm, that'll fit on a single layer, actually; you can use finer wire per layer and connect the layers in parallel then, (It seems, bobbin width is high enough, and turns count low enough, that a series arrangement isn't very practical here after all.) You may consider a smaller core and bobbin set, then, or put additional layers in parallel to further reduce winding losses.

Note that a smaller core will need more turns, so the bobbin fills up quite quickly, and you can't actually go too much smaller before running out of space. If the bobbin is only say 30% occupied on the EER49, it's not that you can go to a 1/3 size core, but more like sqrt(1/3), or probably even less difference, say cubert(1/3) or 70% size. Fortunately, cores are available in lots of sizes, so this isn't too hard to find.

Could also increase frequency and reduce core size a bit that way, but that brings added complications of increased switching loss and strays being more critical. Alternately, can reduce frequency for same core size, increase turns slightly, and relax the design a bit in the same regard.

Also, looking at core loss just now, 200mT is probably a bit aggressive, and 150 or 100 would be more comfortable, at 100kHz. A lower loss material could also be chosen (e.g. TDK N49?). Saturation flux is mostly relevant only to inductors with significant DC bias, or at low frequencies (~20kHz?) where core losses are low enough to push that high.