What is the correct unit to specify throughput of an RTL block? [closed]

Question

There does not seem to be an agreed way to calculate throughput for digital circuit design which is confusing. I am talking about front end design i.e RTL coding. The data rate can be represented as number of bits per clock cycle after an initial latency for pipelined design, or number of bits per second e.g data rate of a serial port.

The difference between the two approaches is that one of these relies on a clock frequency while the other does not. And the thing about clock frequency is that the fmax may be limited by some other part of the system and not the one RTL block of interest that we are designing.

So, this brings me to the question. What is the "correct & standard" way that an FPGA/RTL designer would specify or calculate data throughput?

Answer 1

There is no single answer.

For practical purposes designing a block, bits per clock is most useful because it's technology independent.

Actual performance will then depend on the speed grade of the physical device, which has to be negotiated with the purchasing department.

So I normally use throughput per clock cycle for a technology-independent design, with a representative expected clock speed for a representative device.

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But a system specification must be in throughput per second.

Then implementing a design to meet that system specification using a block, the above figures determine how many times you need to instantiate the block, and the clock speed you can get from synthesis/PAR effort settings, and the speed grades of the FPGA you can afford.

That's just an optimisation problem.

If some other block is limiting the clock rate, then you can either

• improve your block's throughput per clock (most trivially by instantiating 2 of them. Saves engineering cost at the expense of FPGA area cost)
• or doubling your clock (synchronous clocks DO NOT have to impose metastability issues and most toolchains handle the crossings correctly and warn you if they can't)
• or re-pipelining the other block.

But if you can't hit your targets (first, achievability - then, price) you need a better block - perhaps simply a better pipelined version of the same block.

Answer 2

The units depend on the purpose of the RTL block. For an ALU, it might be additions per second. For a shift register, it might be bits per second. For an instruction processor, it might be instructions per second. But you seem to be implying that RTL logic is intimately connected only with input, a view I do not accept. RTL can be involved in retiring instructions, for example, which is more closely related to output than to input.