There does not seem to be an agreed way to calculate throughput for digital circuit design which is confusing. I am talking about front end design i.e RTL coding. The data rate can be represented as number of bits per clock cycle after an initial latency for pipelined design, or number of bits per second e.g data rate of a serial port.
The difference between the two approaches is that one of these relies on a clock frequency while the other does not. And the thing about clock frequency is that the fmax may be limited by some other part of the system and not the one RTL block of interest that we are designing.
So, this brings me to the question. What is the "correct & standard" way that an FPGA/RTL designer would specify or calculate data throughput?