0
\$\begingroup\$

There does not seem to be an agreed way to calculate throughput for digital circuit design which is confusing. I am talking about front end design i.e RTL coding. The data rate can be represented as number of bits per clock cycle after an initial latency for pipelined design, or number of bits per second e.g data rate of a serial port.

The difference between the two approaches is that one of these relies on a clock frequency while the other does not. And the thing about clock frequency is that the fmax may be limited by some other part of the system and not the one RTL block of interest that we are designing.

So, this brings me to the question. What is the "correct & standard" way that an FPGA/RTL designer would specify or calculate data throughput?

\$\endgroup\$
6
  • 1
    \$\begingroup\$ Not sure what you're asking. In general, the throughput requirements are dictated by the application. It's up to the designer to make sure that the throughput of the design is at least that high, through a combination of clock frequency and bits per clock. \$\endgroup\$
    – Dave Tweed
    Commented Jun 19, 2022 at 23:34
  • \$\begingroup\$ So is throughput specified as bits/second of data? In this case throughput and data rate would be the same thing right? I am sure that throughput is not the same thing as data rate. \$\endgroup\$
    – quantum231
    Commented Jun 20, 2022 at 0:55
  • 1
    \$\begingroup\$ So what do you think the distinction is? If I have a math pipeline that can deliver one 16-bit result every clock cycle at 80 MHz, that's 1.28 Gbits/second of data. When would you call that "data rate" and when would you call it "throughput"? Does it matter whether that data is delivered on one wire @ 1.28 GHz or 16 wires at 80 MHz? \$\endgroup\$
    – Dave Tweed
    Commented Jun 20, 2022 at 0:57
  • \$\begingroup\$ Data rate is usually specified at some higher system level rather than a module at very low level of hierarchy. But you are correct, we can use the term and the basic concept for modules at low level of hierarchy. Lets assume that I design a DSP chain, it takes in 64 12-bit values (768 bits) and gives out 20 16-bit values (320 bits). There are more bits going in then coming out. Latency is 10 clock cycles. Now if someone asks me what is throughput, I am not sure what to say. From the answers so far, it seems that reference to a clock frequency is essential to give calculate throughput. \$\endgroup\$
    – quantum231
    Commented Jun 20, 2022 at 1:08
  • \$\begingroup\$ The above questions can be extended by inverting it, i.e 20 16-bit values (320 bits) go in and 64 12-bit values (768 bits) come out; latency is still 10 cycles. \$\endgroup\$
    – quantum231
    Commented Jun 20, 2022 at 1:09

2 Answers 2

2
\$\begingroup\$

There is no single answer.

For practical purposes designing a block, bits per clock is most useful because it's technology independent.

Actual performance will then depend on the speed grade of the physical device, which has to be negotiated with the purchasing department.

So I normally use throughput per clock cycle for a technology-independent design, with a representative expected clock speed for a representative device.


But a system specification must be in throughput per second.

Then implementing a design to meet that system specification using a block, the above figures determine how many times you need to instantiate the block, and the clock speed you can get from synthesis/PAR effort settings, and the speed grades of the FPGA you can afford.

That's just an optimisation problem.

If some other block is limiting the clock rate, then you can either

  • improve your block's throughput per clock (most trivially by instantiating 2 of them. Saves engineering cost at the expense of FPGA area cost)
  • or doubling your clock (synchronous clocks DO NOT have to impose metastability issues and most toolchains handle the crossings correctly and warn you if they can't)
  • or re-pipelining the other block.

But if you can't hit your targets (first, achievability - then, price) you need a better block - perhaps simply a better pipelined version of the same block.

\$\endgroup\$
1
  • \$\begingroup\$ I realized that the throughput can be specified in two ways basically. One is as amount of data per clock cycle and the other as amount of data per unit time. This could be specified as actual data i.e bits, bytes, mega bytes e.t.c or as a more general high level item e.g pixel, image, frame e.t.c. So e.g throughput could be 1 pixel per cycle or 0.5 bytes per cycle e.t.c. Or as in unit time e.g 5 bytes per s, 2 images per ms e.t.c. Both are valid. The actual method used comes down to the application. \$\endgroup\$
    – quantum231
    Commented Jan 2, 2023 at 0:18
3
\$\begingroup\$

The units depend on the purpose of the RTL block. For an ALU, it might be additions per second. For a shift register, it might be bits per second. For an instruction processor, it might be instructions per second. But you seem to be implying that RTL logic is intimately connected only with input, a view I do not accept. RTL can be involved in retiring instructions, for example, which is more closely related to output than to input.

\$\endgroup\$
2
  • \$\begingroup\$ Alright, so throughput is always with reference to time, in that case, we cannot tell about throughput of a design block without also knowing what frequency it shall be run at. Is that correct? Also, what then is the difference between throughput and data rate? I sure they are not one and the same. \$\endgroup\$
    – quantum231
    Commented Jun 20, 2022 at 0:56
  • \$\begingroup\$ Yes, throughout is an amount of something per unit time. The frequency of its operation is inversely proportional to its throughput, provided that the frequency does not get so high that the device cannot keep up. You may then say its bandwidth has been exceeded. Data rate is a specific term for throughout that involves data, say, samples per second or bytes per second. In contrast, you would not normally think of clock edges per second as expressing a data rate. \$\endgroup\$ Commented Jun 20, 2022 at 23:01

Not the answer you're looking for? Browse other questions tagged or ask your own question.