This is something of a half-answer, because you need to do a little more research.
Please remember that, physically, the gate of a MOSFET is a chunk of something (back when I was designing it was silicon-dioxide) that crosses (I hesitate to say "bisect," FETS on silicon can be a lot more complex than that) the doped substrate. As power flows into or out of that very physical something, the electrical barrier is formed or released.
Those gates can take different shapes. In the designs I created, most were a rectangular strip with some height. Some used very narrow strips where speed was more important than a low drain-gate resistance (such as when the FET was used in the logic chain). Others were wider when speed was less important than leakage (such as when FETS were used as active terminal resistances or as part of a current source). Larger MOSFETS would have interdigitated gates (lace your fingers together to see what this would look like). Such a design was meant to reduce the RC charge time and create a more perfect electrical barrier across a larger area of substrate (at the cost of increasing the drain-to-gate resistance) when much larger currents were required in the circuit.
And that's only from the point of view of BiCMOS logic design (what I did) vs. CMOS logic design (probably very similar) or analog circuitry (which can be quite a bit different).
So when you ask about how to identify the "sweet spot," that has more to do with the physical implementation of the MOSFET than it does mathematics. OK, to be fair, it's all still mathematics... you're just not working with the rest of the math that concerns the physical implementation of the gate. That's the part of the research you've not looked into. Keep in mind that when you monkey around with the physical gate implementation, you're not just changing the sheet-rho of the gate, you're also changing the sheet capacitance of the gate. This implies two perspectives that are important: (a) when you charge a gate, time is required to charge the length of the gate (it doesn't charge uniformly or simultaneously) which may or may not be connected to metal on both sides of the gate strip and (b) you're not actually dealing with a resistance, but a reactance. (To make matters even more fun, the electrical barrier isn't a convenient square under the gate. It's more like the bottom of a tea cup, which means the flow of current through the gate is non-linear during the charge/discharge period.)
So, as a conclusion, remember that you're currently working with a simplification that helps you understand the basics of gate operation. But when you start asking about sweet spots, you're entering a larger, more complex world where treating the gate as a simple resistor is no longer valid and the idea of a sweet spot becomes dependent on both the gate's manufacture and the intended purpose of the gate.
To make a long story short, there isn't a single, simple formula or procedure to achieve what you're trying to do. If you ever get a chance, see if you can spend some time with a fabrication facility's chief physicist. They're the people who convert the physics of the physical implementation into models for simulation. An hour with such a person will open your eyes to an entire world that many designers learn little about.
