# How do I get a linear analog output from 8 bits BCD number?

I have two BCD counters I want to get an analog output from, I tried connecting them to a R-2R resistor ladder and it worked, partially, I get +~20 mV on each 1's increase, but when 10's increase I get + 120 mV which isn't linear at all.

Because for instance 30 encoded in BCD is 0011|0000 and not 00011110, I thought I should first convert the BCD integer to binary before feeding it to the ladder but I couldn't find any chip for that purpose, so I would have to implement the reverse double dabble algorithm either with a ton of supplementary components or with a microcontroller (which I don't want to use for this project).

So maybe the simplest solution is a sort of resistor ladder that can convert BCD encoded values to analog in a linear fashion but I could find any on the internet.

I'm kind of stuck right now, it's either that or the reverse double dabble but if you guys have another brilliant idea I'm all ears!

Edit:

@GodJihyo I've implemented the proposed circuit and so far it gives good results like I said about ~25mv for each step which is exactly what I wanted, expect for the 14mv/-114mv step when it comes to the 8's.

To give a bit more context the DAC output will be fed to an op-amp with a thermocouple feedback, in order to drive a heating resistor so I indeed need precise values.

Here's the schematic you asked for note that I directly connected the op-amp output to the inverting terminal since I don't really need amplification, also I used 22k instead of 20k resistors because I don't have 20k resitors, the ratio is slightly changed for the 1's conversion but since it also happen with the 10's and only for the 8 integer it don't think this is the issue.

A buffer would certainly worth a try

I took the measurements before and after the op-amp, results are the same

• Welcome! There are BCD to binary converters available, but this sounds like an ideal case for an MCU with built in DA converter output. Jun 21 at 8:37
• A very warm welcome to the site. Please can you edit your question and add a schematic that includes the values of your R-2R resistors and shows the load on it. Without that, people can really only hypothesise rather than answer your particular question directly. The better the quality of your question, the better the quality of the answers you will attract. Thanks and, again, welcome. Jun 21 at 8:47
• 2 IC needed. susta.cz/fel/74/pdf/DM74184_74185.pdf fig 1 Jun 21 at 8:53
• If the source of your data is a BCD counter, then one obvious solution would be to add a binary counter in parallel with that, connected to the same clock, enable and reset signals. They'll operate in lock-step and the output of the second counter will be the binary equivalent of the BCD value. Jun 21 at 10:00
• Serybva - Hi, your "answer" got multiple flags as it wasn't a new & different solution (which is the only time that you, as the original poster - OP - would write an answer). As well as saying thanks (again, that doesn't belong in an answer on Stack Exchange (SE)) you seem to asking an implied question about your results. Please don't ask questions in an answer on SE either. Perhaps you saw the text entry box below & treated SE like linear forums where you post below everyone else? That's incorrect on SE. Please see the site tour & help center for more rules & etiquette. Jun 21 at 20:58

You can run each digit through a separate R-2R ladder and sum the outputs together scaling the 10s digit to give 10 times the output of the 1s digit.

Here's an example circuit, this gives 100 mV for each step of the 1s digit, and 1 V for each step of the 10s digit, so a BCD input of 1001 0110 would give an output of 9.6 V. You would need to adjust the reference voltage and resistor values to your particular circumstances.

I used an LT1007 opamp in the simulation simply because it was one available by default in LTspice, it should be able to be replaced with most general purpose opamps.

The voltage for Logic1 was chosen as 1.6V so that the 16 steps each divider is capable of would give a round number, either 100 mV or 1.0 V, for each step. To scale it for other voltages you can adjust the gain of the opamp by changing the feedback ratio.
To do this use this formula to calculate the value for the resistor from the inverting input to ground which is R2 in the schematic. $$R2 = \frac{R17}{(17.6/V_{Logic1})-1}$$ Example for Logic1 = 5 V:

$$\frac{10000~\Omega}{(17.6 / 5~V)-1} = 3968.25~\Omega$$

Using that value for R2 should give 100 mV steps with 5 V logic inputs. Of course you would use a fixed resistor in series with a pot to adjust it exactly, 3.9K with a 100 ohm trimmer would do it.

The precision of an R-2R DAC depends on the input voltages, which are going to depend on what's driving it. The best precision would be to use relays which would have almost no voltage drop.

Driving it with the outputs of an IC is going to be less precise because the outputs are not going to go completely to 0 V or Vdd. A counter like the CD4510B with a Vdd of 5 V might go from 0.4 V to 4.6 V. Adding a buffer like the 74HC244D might get you 0.2 V to 4.8 V or better.

If you don't need precise output values and are just looking for a linear output this shouldn't matter too much, but if you want precision you need to drive it with low impedance sources.

• One could add an arbitrary number of decimal stages, using four resistor values total, if the most significant four-bit 1K/2K stage was connected to the output, each stage other than the least significant stage was connected to the one before via 8.10K resistor, and the last stage was connected to ground via 9.00K resistor. Output equivalent resistance would be 900.0 ohms. If the logic signals feeding the DAC swing 5.00 volts, each step in the most significant digit would be 4.5/16 volts; each step in the next most significant digit would be 4.5/160 volts, then 4.5/1600, etc. Jun 21 at 18:23
• How does this work? Both circuit groups use the same resistor values, while your text says that for some reason the left group contributes 1V per bit, while the right group contributes 0.1vV per bit Jun 22 at 7:30
• Thank you, it works, however I get a strange behavior when unit digit is 8 the step is only 14mv, when the ten's digit is 8 the step is -144 mv while I get a mean 25mv step for any other number Jun 22 at 9:04
• @Ferrybig The resistor values for the 1s (10K/20K) are 10 times the values for the 10s (1K/2K). Jun 22 at 10:44
• @Serybva I'll take a look at it again when I get to work in a couple of hours. I changed it based on a previous comment and checked a few values with it but didn't do an exhaustive test. Jun 22 at 10:49

There are at least three ways I can think of.

• Modify an R-2R ladder for BCD weighting. Conceptually it's straightforward enough, but I don't want to wrap my head round the math now. I'll let another contributor sort that one out.
• Use two 4 bit R-2R ladders, and add them together, scaling their outputs in a 10:1 ratio.
• As you only have 8 bits to convert, it's straightforward enough to use single resistors for weighting, as the dynamic range is not huge. For instance, take the '1' bit through an 800k resistor, the '2' through a 400k, and so on through to the '80' bit using a 10k resistor. All resistors are then connected to a common point. The current through each resistor represents its weight. You could take the common junction to a virtual ground amplifier, for a low impedance voltage output. You could also take the voltage output directly from the common point, which will have a drive impedance of rather less than 10k, and will swing rail to rail when not loaded.

I'll leave it as an exercise for the reader to show that the third option, even without the virtual ground amplifier, gives a linear output, regardless of load impedance (as long as it's driven from CMOS (or other 'low output impedance in both states' technology) and into a linear load).