As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what happens with slower devices such as SPI?
If the SPI clock signal is kept high at all times except when the device in question is going to send data, would it be acceptable to gate it? (
ss | sck, to keep some of all the slaves except from 1 disabled).
I don't see how there could be a clock skew problem, given that this clock will be used only by one master and the enabled slave at each time.