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As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what happens with slower devices such as SPI?

If the SPI clock signal is kept high at all times except when the device in question is going to send data, would it be acceptable to gate it? (ss | sck, to keep some of all the slaves except from 1 disabled).

I don't see how there could be a clock skew problem, given that this clock will be used only by one master and the enabled slave at each time.

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  • \$\begingroup\$ Not only acceptable, that would be the right thing. \$\endgroup\$
    – TQQQ
    Jun 21, 2022 at 17:21
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    \$\begingroup\$ What model of FPGA are you using? In Xilinx 7-series FPGAs there is a BUFG primitive that has a CE (clock enable) pin specifically designed for clock gating. \$\endgroup\$
    – user4574
    Jun 21, 2022 at 17:24
  • \$\begingroup\$ I'm using Basys 3 \$\endgroup\$
    – Martel
    Jun 21, 2022 at 18:34

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If you look at any SPI device, they don't even expect or require a running clock. The clock might be even gated internally by SS. So SPI bus may tolerate a continuous clock and may be compatible with it, especially if SS is enabled at correct phase and with proper setup and hold timing.

Having just a clock for SPI bus is completely different thing compared to an FPGA clock signal.

For SPI, it's just one generic data pin among others, even if it is used for synchronous communication on the other SPI wires.

For FPGA, clock pins have special handling inside the FPGA with direct wiring and strong buffers for distributing the clock signal accurately to logic cells that need a sharp well defined clock to make all logic cells tick with the same clock.

So for an FPGA, the SPI clock would just be a generic data pin among other SPI data signals, either sampled or generated by using the FPGA clock.

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  • \$\begingroup\$ Does the FPGA consider a clock signal only the one it automatically generates? (in my case, Basys 3, its 100 MHz clock signal). Does that mean that I'm fine gating any clock, as long as I'm sure there cannot be clock skew problems because it is very slow? \$\endgroup\$
    – Martel
    Jun 21, 2022 at 18:07
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    \$\begingroup\$ @Martel pretty much. Maybe don't think of it as "don't gate clocks" but "there is already super fast super efficient wiring to get clocks everywhere and if you don't use it you're wasting performance". I don't know which FPGA you are using, but the one I am using has this primitive called GBUF (I think?) which allows you to send any signal into the clock distribution wiring. \$\endgroup\$
    – user253751
    Aug 3, 2022 at 20:18

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