How does a bootstrap capacitor power the gate?

Question

I understand this circuit for the most part, but I am still confused on something.

So lets say that the bootstrap capacitor is already charged from the bottom MOSFET being on previously. Then, a logic level signal is applied to HI (pin 2) which initiates the capacitor to unload on the gate through the path highlighted in red. This turns the gate of the MOSFET on and because the negative terminal of the bootstrap capacitor is connected to the source of the top MOSFET, the Vgs stays high enough to keep the gate on.

I know that this works, I just don't understand how one part of it works.

The part I don't understand is how the high voltage is getting to the gate. It seems that the only possible way would be from the source of the top MOSFET and through the bootstrap capacitor, which could make sense because the source of the MOSFET is emitting square waves. I see in many circuit designs that the bootstrap capacitor is polarized. Wouldn't that mean that the high voltage coming from the source of the MOSFET would get blocked by the bootstrap capacitor? If that were true then the MOSFET gate wouldn't stay open.

That's my issue, I just don't get how the high voltage is getting to the gate if the bootstrap capacitor is polarized.

Answer 1

Current does not need to flow from the high voltage to the gate.

What matters is the bootstrap cap has 10-20V across it and is placed across gate-source so the MOSFET can switch no matter what the gate or source voltage is when measured relative to ground.

I think you're confusing things between voltage and current.

Answer 2

Bootstrap capacitor is charged via diode and Q2.

When the low transistor Q2 is turned on by PWM2, the SW/HS node with bootstrap cap negative is connected to ground. Then current will flow from VDD supply via Rboot and Dboot into Cboot positive terminal, charging it up to VDD.

Later on when PWM2 is turned off, the cap remains charged, and when PWM1 turns on, the HB is connected to HO and the Q1 turns on. SW/HS node rises to VDD and because Cboot is still charged the capacitor makes the HB supply and HO gate drive 2×VDD, except some charge was consumed to turn on Q1. The cap will again fully charge when Q1 is off and Q2 is on.

The cap can be polarized as the upper terminal will always be more positive than the lower terminal. If a polarized cap is used it must be correctly mounted. Usually ceramic caps are used because they have better properties and are much smaller, and even the orientation does not matter as they don't have a polarity.