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I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. enter image description here

Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at the nodes. I have chosen A=1.8 and B=1.8 , so output should have been 1.8 V but I am getting 1.24 V as can be seen from the schematic. For A=0V , B=1 V , Output is 1.01 V which is wrong.

The situation worsens when I use other A and B combinations.

Can anyone help me out in getting full rail to rail voltage swings at the output?

enter image description here

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  • \$\begingroup\$ Why is the output of the first inverter (the one generating A bar) is at 600mV instead of 0v ? I think you got some sizes wrong. \$\endgroup\$
    – Mike
    Jun 22 at 12:34
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    \$\begingroup\$ Why do you have all of your substrate connections tied to the transistor sources? All N-channel substrates should be "gnd" and all P-channel substrates should be "vdd". \$\endgroup\$
    – Dave Tweed
    Jun 22 at 12:35
  • \$\begingroup\$ Looks like you mixed up N and P MOSFETs by mistake. \$\endgroup\$
    – Mitu Raj
    Jun 22 at 14:31
  • \$\begingroup\$ @DaveTweed This solved the issue. Thank you! Can you tell me why this made the swings so less? \$\endgroup\$ Jun 22 at 19:46
  • \$\begingroup\$ @SouhardyaMondal lookup Body Effect \$\endgroup\$
    – Mike
    Jun 22 at 21:15

1 Answer 1

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Why do you have all of your substrate connections tied to the transistor sources? All N-channel substrates should be "gnd" and all P-channel substrates should be "vdd".

Remember, it's the gate-to-substrate voltage that determines the state of the channel in a MOSFET. In integrated circuits, the substrates for N-channel devices are always tied to the most negative node, and the substrates for P-channel devices are always tied to the most positive node.1

Otherwise, if the substrate is connected to the source terminal, it becomes difficult to turn the transistor fully on if the source terminal is not at a fixed voltage. This is normally done only in discrete MOSFETs, and these must be driven by a gate signal that is referenced to the source terminal.


1 Note that in addition to having better control of the transistor characteristics, this also makes sure that the isolation among the multiple transistors on a single piece of silicon works properly.

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  • \$\begingroup\$ But in this case , the MOSFETS will suffer from body effect which can vary the threshold voltage (Vt) of the transistor, wouldn't it be a problem in this case? \$\endgroup\$ Jun 24 at 11:22
  • \$\begingroup\$ But that's precisely the point -- in digital design, especially when using transmission gates, you WANT the threshold voltage to be relative to the body (substrate), not the source. With your original circuit, it is the threshold voltage that is killing your logic levels. \$\endgroup\$
    – Dave Tweed
    Jun 24 at 11:58
  • \$\begingroup\$ Now I get it. Really thankful to you for taking the time to explain :) \$\endgroup\$ Jun 24 at 13:58

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