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VHDL has a while loop but not a do-while loop. In the do while loop the code inside the loop is always executed atleast once since the condition is evaluated at the end of the loop rather than the start.

Is it possible to implement do-while loop in VHDL? I need this for simulation testbench.

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2 Answers 2

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While less compact than do-while, VHDL does contain the loop-exit-end loop construct that lets you exit a loop wherever you like. So you're not restricted to ending the loop before one pass or after one pass.

(Many or no lines can go in place of ... in these examples.)

  loop
     ...
     exit when (cond);
     ...
  end loop;

If your simulation testbench/model gets longer, it's often useful to label the loop so you can follow it more clearly. That also lets exit come out of as many levels of a nested loop as you like.

  Outer : loop
    ...
    Inner : loop
      ...
      exit Outer when (cond);
      ...
    end loop Inner;
    ...
  end loop Outer;
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    \$\begingroup\$ You might note that in (cond) that the parentheses are not required but are only there for readability. \$\endgroup\$
    – Jim Lewis
    Jun 22, 2022 at 13:37
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You could use an infinite loop and exit at the end condition; that's the clearest way.

Otherwise put the code in a function/procedure (if feasible) and call it once before the while and once inside the loop, that's the elegant way.

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  • \$\begingroup\$ I am using the infinite loop approach, so my suspicion was correct that the two methods you mentioned are the only ones that I could possibly use. \$\endgroup\$
    – gyuunyuu
    Jun 22, 2022 at 10:01
  • \$\begingroup\$ given that VHDL comes apparently from Pascal/ADA (Verilog is more of the C family) I would expect some repeat/until construct in it. AFAIK there is not, so these are the usual solution (there are theorems for the conversion proof but it's intuitive enough) \$\endgroup\$ Jun 22, 2022 at 10:04
  • \$\begingroup\$ It would be nice to answer with code rather than words. See Tony's answer below. \$\endgroup\$
    – Jim Lewis
    Jun 22, 2022 at 13:36

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