How to implement do-while loop in VHDL?

Question

VHDL has a while loop but not a do-while loop. In the do while loop the code inside the loop is always executed atleast once since the condition is evaluated at the end of the loop rather than the start.

Is it possible to implement do-while loop in VHDL? I need this for simulation testbench.

Answer 1

While less compact than do-while, VHDL does contain the loop-exit-end loop construct that lets you exit a loop wherever you like. So you're not restricted to ending the loop before one pass or after one pass.

(Many or no lines can go in place of ... in these examples.)

  loop
     ...
     exit when (cond);
     ...
  end loop;

If your simulation testbench/model gets longer, it's often useful to label the loop so you can follow it more clearly. That also lets exit come out of as many levels of a nested loop as you like.

  Outer : loop
    ...
    Inner : loop
      ...
      exit Outer when (cond);
      ...
    end loop Inner;
    ...
  end loop Outer;

Answer 2

You could use an infinite loop and exit at the end condition; that's the clearest way.

Otherwise put the code in a function/procedure (if feasible) and call it once before the while and once inside the loop, that's the elegant way.