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I have DMM which is producing pulse with duration of around few microseconds. The pulse need to be sampled in PLC, which has sampling rate of 1ms. In other words the cycle loop can't be reduced to microsecond resolution. So it's impossible to reliably detect the pulse from DMM.

Could somebody recommend a simple TTL based circuit solution, which will be able to capture that microsecond resolution pulse and convert it into millisecond resolution pulse?

I

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    \$\begingroup\$ Looks like a duplicate by the bottom-line requirement: electronics.stackexchange.com/questions/30689/… \$\endgroup\$
    – Eugene Sh.
    Jun 22 at 17:00
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    \$\begingroup\$ @Bryan to be completely fair, dropping in a 1€ microcontroller + 1 decoupling capacitor vs designing a monostable using a 555 + N passives: I don't see the 555 being the less heavy duty solution, especially if this is a one-off! \$\endgroup\$ Jun 22 at 17:48
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    \$\begingroup\$ @MarcusMüller Indeed! the debate of 555 vs microcontroller is largely an ethical one - "Do I feel comfortable using a better computer than I had in 1996 to make a 1us pulse a 10ms pulse?". I'm generally in favour of expedience; whatever is closest at hand it going to get spliced into circuit. \$\endgroup\$
    – Bryan
    Jun 22 at 18:04
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    \$\begingroup\$ One has to consider what putting a 1 euro MCU additionally needs. A place to put it, something to give it power, connectors to attach to outside world and someone to make the program. Maybe a clock source. Writing the program needs tools. Downloading the program needs tools. It might be worth it to just buy something where those have been taken care of (even if it means an Arduino or similar ready made board). \$\endgroup\$
    – Justme
    Jun 22 at 18:12
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    \$\begingroup\$ LOL. I wonder if in the near future we are going to have a similar dilemma: "Do I feel comfortable using an AI which is smarter than any human to extend the pulse" :D \$\endgroup\$
    – Eugene Sh.
    Jun 22 at 18:12

5 Answers 5

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TTL solution with active low input and output. R and C are calculated for 2ms output pulse width.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Strictly speaking, a HC type chip will not be a TTL compatible solution. Does it come in HCT type? \$\endgroup\$
    – Justme
    Jun 22 at 19:52
  • \$\begingroup\$ @Justme Yes, there is a HCT version, same RC timing, I will update the schematic \$\endgroup\$
    – Jens
    Jun 22 at 20:04
  • \$\begingroup\$ @Justme What are the implications in case of using non TTL compatible chip? \$\endgroup\$
    – Pablo
    Jun 22 at 20:04
  • \$\begingroup\$ @Pablo Then it won't be compatible with TTL levels, and you say your devices work with TTL levels. But it can be worked around with a simple resistor. \$\endgroup\$
    – Justme
    Jun 22 at 20:11
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Here's an example using a 555 timer in monostable mode. R1 and C1 form the timing network that control the output pulse duration, the output pulse will be \$t_{pulse}=1.1RC\$ . R3 is a load resistor to make the simulation work, that would be your PLC in this case, and CLK1+NOT1 are the signal source (10Hz with a 1us duty cycle) which in this case is your meter. C2 is for stability, it decouples the internal divider reference ladder somewhat.

schematic

simulate this circuit – Schematic created using CircuitLab

Here is a plot of the waveforms from this simulation:

input waveform from monostable 555 cct

output wavefrom from monostable 555 cct

For reference I pulled the design from this website, which goes into far greater detail about the operation of the timer itself:

https://www.electronics-tutorials.ws/waveforms/555_timer.html

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This is not a pulse extension problem/solution, rather it is a memory issue to tell the PLC that there was a new ADC conversion pulse, then the PLC responds to clear that latch when it is ready and sees the ADC ready output =1.

Set + Reset functions active low can be implemented a variety of ways. This is also called a "pulse-triggered handshake" like REQ/ACK

schematic

simulate this circuit – Schematic created using CircuitLab

This way you are guaranteed to stay in sync if your PLC can keep up to readings at the ADC rate without having to guess or miss a new reading. This way the PLC can sample at >= the ADC rate and not 2x the ADC rate as in Nyquist theory as there is a 1 bit memory involved.

Stock 2 input 5V NAND Gate choices.

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  • \$\begingroup\$ Neat idea to latch the pulse and to have request/acknowledge signals. I was a bit shy and did not suggest it, but if modifications to PLC can be done, I would have just suggested a toggle flip-flop and checking if PLC input has changed state. Assuming the pulses don't appear so often that PLC misses them. \$\endgroup\$
    – Justme
    Jun 22 at 19:58
  • \$\begingroup\$ Latching was considered initially, but it makes the problem overcomplicated and I need to allocated another PLC output. Besides the rep rate is hundreds of ms, so PLC should be able to detect the edge of pulse with duration > cycle time reliably. \$\endgroup\$
    – Pablo
    Jun 22 at 20:01
  • \$\begingroup\$ Do you care if PLC reads old data from some long 1-shot? why not do this synchronously as shown. You should not need 2 PLC's to read an ADC result \$\endgroup\$ Jun 22 at 20:27
  • \$\begingroup\$ I do care of course not to read the old data. It's not 2 PLC, but allocating extra output in PLC terminals. This is scarce resource in our system. The chance that I read old data is very small as the signal is repeating with more or less fixed duration and the gap between pulses are big enough. Nevertheless, may I ask which NAND chips supporting TTL would you recommend? \$\endgroup\$
    – Pablo
    Jun 22 at 20:36
  • \$\begingroup\$ That depends what logic voltage you use. If <=5V any NAND gate will do and there are dozens of types. \$\endgroup\$ Jun 22 at 20:39
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Instead of pulse extension, I suggest using a 1-bit counter (i.e., a toggle flip-flop, which you could make with a D flip flop and an inverter if you have to) that changes state every time it is clocked by a DMM pulse.

You can then use your PLC to detect when it's state is different from the previous sample.

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  • \$\begingroup\$ Interesting. Could you post a reference circuit with components? \$\endgroup\$
    – Pablo
    Jun 23 at 6:00
  • \$\begingroup\$ You could use half of a single 7474. Just wire ~Q -> D, input to CLK and output at Q \$\endgroup\$ Jun 23 at 11:57
  • \$\begingroup\$ A variation on this which can be even better is to use a pair of one-bit registers, one of which is clocked by the signal to be detected and the other of which is clocked by an observer. Wire the non-inverting output of the first to the data input of the second, and the inverting output of the second to the data input of the first. Any time the outputs differ, that means an event was observed since the last acknowledgment was received. If the outputs match, that means an acknoweldgment was received since the last event was detected. \$\endgroup\$
    – supercat
    Jun 23 at 20:26
  • \$\begingroup\$ @supercat If you wanted to spend a PLC output on this, then you would use just one flip-flop and wire that output to D. \$\endgroup\$ Jun 24 at 2:21
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Maybe a diode, capacitor, and resistor?

Low input pulse would discharge the capacitor via diode.

A high input would then allow the capacitor to slowly charge back to high voltage again.

In addition a simple 74HCT14 inverter chip could be used as a buffer to drive the RCD network and again buffer the RCD output to square wave.

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  • \$\begingroup\$ Charge time to discharge time is 1:500 minimum, not so easy. TTL input feeds 1-2 mA, so we would need 0.5-1A for 2us. \$\endgroup\$
    – Jens
    Jun 22 at 18:46
  • \$\begingroup\$ @Jens Of course a TTL compatible buffer can be used, or maybe a 74HCT14 schmitt trigger inverter. It has definite input and output impedances and will square up the RC waveform nicely. \$\endgroup\$
    – Justme
    Jun 22 at 19:42
  • \$\begingroup\$ @Jens could you please show a circuit with 74HCT14? \$\endgroup\$
    – Pablo
    Jun 22 at 20:03
  • \$\begingroup\$ @Pablo: I can't do this as a blind shot with a function guarantee using a 74HCT14. Ask Justme. \$\endgroup\$
    – Jens
    Jun 22 at 20:19
  • \$\begingroup\$ Oops, sorry Jens :) \$\endgroup\$
    – Pablo
    Jun 22 at 20:26

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