Can I dynamically change the input clock frequency of the AT91SAM3X8E?

Question

Background:

I'm attempting to use an AT91SAM3X8E microcontroller (for Arduino Due compatibility) to create a USB to \$I^{2}S\$ interface. Most \$I^{2}S\$ CODECs require a master clock that is \$MCLK=256*BCLK\$ where BCLK is the bit clock, which in turn is \$BCLK=64*F_{s}\$. This would be trivial to generate if I was only dealing with one sample frequency, but I would like to retain compatibility for all common values (44.1kHz, 48kHz, 88.2kHz, 96kHz, 196kHz).

I plan to use the microcontroller's Synchronous Serial Controller (SSC) for this task, which it seems very well suited for.

Problem:

All of the \$I^{2}S\$ clock signals must run off of a multiple of the sampling rate, which varies between two sets - multiples of 44.1kHz and multiples of 48kHz. This means that the clock driving the serial controller must be dynamically switched between two values. At first, I thought that driving the serial controller's transmit clock with the appropriate frequency would be the best option, but that doesn't allow for dynamic clock division for supporting different sampling frequencies. I concluded (perhaps incorrectly) that I need to be able to switch the master clock of the microcontroller in order to address all of these issues.

Question:

Can the AT91SAM3X8E support dynamically changing the clock that it receives on the XIN pin or would that cause run-time errors? If so, would there be a way to get around those (such as temporarily using the RC oscillator)?

Answer 1

I don't know anything about the AT91SAM3X8E specifically, but I'll guess an answer based on my knowledge of ICs.

Theoretically, there's no reason why you wouldn't be able to dynamically change the master clock frequency in a digital circuit. What you have to be careful of is that during the switching you cannot have any two successive rising edges that violate the maximum frequency of the device. If you imagine switching from one waveform to another when the 'switched from' clock is falling and the 'switched to' clock is rising, then you could get a clock period for one cycle which could be much less than the period of either clock. This would blow the timing on several of the paths and leave your micro in an illegal state.

If you have some way to guarantee that you can properly synchronize the transition between the clocks without creating such a pulse, I can't think of any problem with it.