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I found this schematic for an AVR programmer with a level shifting buffer: LV-USBasp schematic

The Vcc of the target is supplied at the VCCIO pin and the 5V levels of the ATmega8 need to be converted to logic levels that won’t fry components in the potentially lower voltage target. In this circuit, this is done by a 74HC541 buffer IC that is powered from VCCIO. If the target only supplies e.g. 3.3V, then the signals from the uC to the target will be at 3.3V levels. One of the signals goes from the target back to the uC. The same buffer IC is used (A8→Y8), which works out as long as VCCIO is high enough that the buffer output is still recognised as High by the uC. Here is a magnified view of the level shifting circuitry: Level shifting part

Now what I wonder about is the network of resistors and capacitors around the 74HC541. I have, ummm…, experimentally confirmed that the 680ohm resistors on the left, R7, R9, R10 need to be there because of the input protection clamping diodes in the IC. Without them, a 5V high output from the uC gets shorted to the lower VCCIO supply though the clamping diode.

R8 and R11 are possibly short circuit protections? But why is there none on Y3–Y5, the target reset?

And maybe most of all: what is the point of the 330p capacitors to ground on most of the lines, but not the reset one? (Not reset: maybe because it is pulled low at the beginning of the programming procedure and stays there until it’s done?)

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    \$\begingroup\$ I'm guessing they are filter/de-bounce so you have nice smooth edges as you pass through the logic threshold, since providing current to the HC541 supply through one of the protection diodes on an input will cause the output levels to shift slightly. The reset circuit in your target likely has its own capacitor and is probably not prone to problems from glitches. \$\endgroup\$ Jun 23, 2022 at 12:28
  • \$\begingroup\$ Yes… my ‘experiments’ (i.e. connecting things without the 680ohms and wondering where the heat comes from) certainly confirm that the VCCIO shifts quite a bit. So 330p would help while not slowing down transmissions too much. There’s also typically a length of flat cable between your programmer and the target, so that could pick up noise. But for most of the signals a cap on the target side would be more sensible then, right? \$\endgroup\$
    – mabartibin
    Jun 23, 2022 at 12:55
  • \$\begingroup\$ Capacitor on the target reset… yeah, Arduinos have one to reset into the bootloader, but AVR circuits in general don’t, as far as I have seen. So my bet is still that it’s not needed because it only goes low and then stays there for a couple seconds until the whole process is over. \$\endgroup\$
    – mabartibin
    Jun 23, 2022 at 12:57
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    \$\begingroup\$ I agree with you - as close to the inputs as possible. \$\endgroup\$ Jun 23, 2022 at 13:30
  • \$\begingroup\$ @mabartibin I'll look at it later, sometime. But you have posed a well-framed question, I think. So +1 for now. \$\endgroup\$
    – jonk
    Jun 24, 2022 at 8:22

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Now what I wonder about is the network of resistors and capacitors around the 74HC541. I have, ummm…, experimentally confirmed that the 680ohm resistors on the left, R7, R9, R10 need to be there because of the input protection clamping diodes in the IC. Without them, a 5V high output from the uC gets shorted to the lower VCCIO supply though the clamping diode.

Yes, the internal protection diode of the 74HC541 will clamp the voltage to roughly one forward-bias voltage of a diode above the VCCIO. The resistors are needed to limit the current to a safe level. 74HC541 has absolute maximum input/output clamping current of ±20mA. So with a 680Ω and a voltage difference of 1.7V, the clamped current is 2.5mA. There are 4 such connections with a total of 10mA, which is well below 20mA limit. Maybe one 74LV4T125 for down translation and one 74LV1T125 for up translation and minus the resistors and pull-up would be more ideal solution. The 74HC541 is probably not the best solution, but if cost and availability is an issue you tend to abuse a bit, but within the allowable limit, to get the job done.

If the target only supplies e.g. 3.3V, then the signals from the uC to the target will be at 3.3V levels. One of the signals goes from the target back to the uC. The same buffer IC is used (A8→Y8), which works out as long as VCCIO is high enough that the buffer output is still recognised as High by the uC.

3.3V is high enough for ATmega8, but not for ATmega48. According to the ATmega8 specs, a high is only guaranteed if it exceeds \$ 0.6 \times V_{cc} = 3V \$, but a guaranteed high for ATmega48 requires the voltage to exceed \$ 0.7 \times V_{cc} = 3.5V \$. Resistor R14 (3kΩ) is there to pull the voltage up a tiny bit just so it is \$ 3.3 + \frac{680}{3680} \times (5 - 3.3) \approx 3.6V\$ when driven high. And at the same time not violating \$ \left( \frac{680}{3680} \times 5 \approx 0.93V \right) \$ the guaranteed low for ATmega8 when driven low, which needs to be below \$ 0.2 \times V_{cc} = 1V \$. (A guaranteed low for ATmega48 is below \$ 0.3 \times V_{cc} = 1.5V \$)

R8 and R11 are possibly short circuit protections? But why is there none on Y3–Y5, the target reset?

Normally the 100Ω resistors like R8 and R11 are for impedance matching of possibly long external wires connected to the CON3 to reduce and/or eliminate reflections if the other ends are not or poorly terminated. But here they are paired with 330pF capacitors and most probably intended to damp the signals (see further comment below). By the way, damped signals are not going to reflect, if sufficiently damped. Y3-Y5 signal comes from SS (slave select) pin of the MCU. It is not a reset pin. The missing resistor after the Y3–Y5 most likely is to save cost/space or the designer figured that it is OK to leave it out. SS is toggled pretty infrequently than the MISO/MOSI lines and any ringing on rising/falling edges (due to impedance-mismatched reflections) die down long before the immediate next rising/falling edges. Also, with the 3 output drivers banded together can strongly suppress the incoming reflections.

And maybe most of all: what is the point of the 330p capacitors to ground on most of the lines, but not the reset one? (Not reset: maybe because it is pulled low at the beginning of the programming procedure and stays there until it’s done?)

By the arrangement of the capacitors and resistors, I guess the capacitors act as signal damper to slow rise/fall time of the signals (that are going out, MOSI & SCK, and coming in, MISO) to reduce EMI, crosstalk, and signal reflections (especially with long external wires). The capacitors can also act as poor ESD suppressors, but TVS devices would be more appropriate for such thing and if present they should be placed very very close to the CON3 to be effective. (Note again that SS is SPI slave select, not reset).

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  • \$\begingroup\$ Thanks, a really excellent answer! I was referring to the "reset" signal since the SS of the controller is connected to the reset pin of the programmed device. Indeed, this is a slow signal so that explains why the damping is not necessary on that one. \$\endgroup\$
    – mabartibin
    Feb 6 at 8:36

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