Probably because of this note at the bottom of page 4 in the datasheet:
The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.
Note that the acquisition time is fixed at 1200 ns, but the conversion time varies from 500 to 8800 ns, so the conversion time likely includes the wake-up latency.
A rising edge on CONVST (conversion-start) tristates DOUT, samples the input signal, and puts the ADC into conversion mode. Conversion itself is done with the internal clock, but the entry into conversion mode must include powering on the device.
This is confirmed in the "Power Saving" section on page 24 of the datasheet:
The device has an auto power-down feature that powers down the internal circuitry at the end of every conversion. Referring to Figure 54, the input signal is acquired on the sampling capacitors when the device is in a power-down state (tacq); at the same time, the result for the previous conversion is available for reading. The device powers up on the start of the next conversion. During conversion phase (tconv), the device also consumes current from the reference source (connected to pin REF).
The conversion time, tconv, is independent of the SCLK frequency. When operating the device at speeds lower than the maximum rated throughput, the conversion time, tconv, does not change; the device spends more time in
power-down state. Therefore, as shown in Figure 55, the device power consumption from the AVDD supply and the external reference source is directly proportional to the speed of operation.
It does not appear that there is any way to disable this auto power-down feature, so you're stuck with this variable conversion time.