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In the ADS8867 datasheet it says:

Conversion duration may vary but is bounded by the minimum and maximum value of tconv, as specified in the Timing Characteristics section. (p.18)

The conversion time is given as 500 to 8800 ns (p.5).

If there is an internal clock for conversion, which I suppose has a fixed frequency, why is the conversion time range so wide?

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2 Answers 2

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Probably because of this note at the bottom of page 4 in the datasheet:

The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.

Note that the acquisition time is fixed at 1200 ns, but the conversion time varies from 500 to 8800 ns, so the conversion time likely includes the wake-up latency.

A rising edge on CONVST (conversion-start) tristates DOUT, samples the input signal, and puts the ADC into conversion mode. Conversion itself is done with the internal clock, but the entry into conversion mode must include powering on the device.

This is confirmed in the "Power Saving" section on page 24 of the datasheet:

The device has an auto power-down feature that powers down the internal circuitry at the end of every conversion. Referring to Figure 54, the input signal is acquired on the sampling capacitors when the device is in a power-down state (tacq); at the same time, the result for the previous conversion is available for reading. The device powers up on the start of the next conversion. During conversion phase (tconv), the device also consumes current from the reference source (connected to pin REF).

The conversion time, tconv, is independent of the SCLK frequency. When operating the device at speeds lower than the maximum rated throughput, the conversion time, tconv, does not change; the device spends more time in power-down state. Therefore, as shown in Figure 55, the device power consumption from the AVDD supply and the external reference source is directly proportional to the speed of operation.

It does not appear that there is any way to disable this auto power-down feature, so you're stuck with this variable conversion time.

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I'm currently using the Texas Instruments ADC ADS8861, which is very similar to yours in terms of this variable conversion time.

My best guess here is, that the frequency of the internal clock, even if it is fixed, has a rather high tolerance (from chip to chip) due to manufacturing tolerances. Furthermore, I would expect that the clock frequency is also dependent on the ambient temperature during operation.

I think that the \$t_{CONV}\$ variation on the datasheet is just the consequence of these frequency variations of the internal clock (Power-Up time might be variable too).

However, if you look at a single ADC at const. temperature, I expect that the conversion time should be pretty much constant during consecutive samples.

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  • \$\begingroup\$ That was my first guess, too, but if that's true, they wouldn't be able to give a fixed acquisition time of 1200 ns. I checked the datasheet for a histogram showing the clock-frequency distribution across parts, but that isn't included here for whatever reason. Have you actually clocked your ADS8861 to verify that the conversion time is constant across samples? \$\endgroup\$
    – Cody Gray
    Jun 26 at 13:40
  • \$\begingroup\$ No the acquisition time is not fixed. Its 1200ns min. and its mainly limited by the SPI clock speed (max 16MHz) that is used to read the 16bits. The only thing that actually is fixed is the conversion time (500ns to 8800ns). The sampling rate of the ADC is then the conversion time (max 8800ns) + the acquisition time (min 1200ns) = 100kSPS max. However, you are free to lower the sampling frequency with the advantage that the acquisition time increases (more time for SPI transmission). \$\endgroup\$
    – Mau5
    Jun 26 at 13:58
  • \$\begingroup\$ @CodyGray No I have not checked that because I don't have my circuit on a PCB yet \$\endgroup\$
    – Mau5
    Jun 26 at 15:42

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