I would like to have the possibility to select between two main clock on my STM32. Both clock are single ended, 3V3 LVCMOS output. First clock is a 19.2 MHz TCXO, and second clock is a variable clock generator at 10 MHz max. The STM32 is powered at 3V3 and HSE is in pass through.

I found a chip like 74AUP1G157 but I 'm not sure if I read the datasheet correctly about bandwidth limit (max frequency I can pass through this chip).

I will put one clock on I0, the second on I1, the STM32 clock input pin (OSCIN) on Y and I will toggle the S input with GPIO. (I have no problem configuring STM32 internal PLL, switching back MSI, etc...)

Verity table

I want to be sure what is the 74AUP1G157 bandwidth and more generally understand how to get the bandwidth limit on an "multiplexer" component.

On this kind of device I only see a time dependent parameter called "Propagation delay" (Tpd) depend on output capacitance. For example if I take the worst case output capacitance CL = 30 pF at 3V3 I can get Tpd = 6 ns (25°C)

Propagation delay at 30 pF capacitance

To get the maximum bandwidth in this context, I would like to do :

F = 1 / Tpd  
F = 1 / 6 ns
F = 166.7 MHz  

I probably need to get a security factor like 2 or more :

Fmax = 0.4 x F  
Fmax = 0.4 x 166.7 MHz  
Fmax = 66 MHz  

With this chip, I can probably safely pass 66 MHz clock signal through this multiplexer. (at 25°C, Vcc = 3V3 and track impedance between this chip and STM32 dont exceed 30 pF)

Is my reasoning correct or did I not understand anything about multiplexer bandwidth ?
(In case of NO, can you help me to understand how to find the bandwidth limit of a multiplexer ?)



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