The overarching concern is efficiency. To avoid significant losses you would prefer to have no current with full voltage across the collector and emitter (transistor off), or full current and no voltage across the collector and emitter (transistor on). This requires operating the transistor in full off and full on, avoiding dwelling in the linear region in between. If you drive the base with a sinusoidal input, you are not avoiding the linear region very well. So a common approach is to use a pulse-width-modulated (PWM) input to the base. Then the transistor is fully on or fully off, but the duty cycle can be varied in a sinusoidal manner, resulting in an average voltage and an average current that vary sinusoidally, but without incurring unacceptable efficiency losses.
One good way to generate a PWM input whose duty cycle varies sinusoidally is to use a processor to increase an angle linearly and a trigonmetric function (sine) to convert this to a sinusoid. Then use the magnitude of the sinusoid to select a duty cycle. An easy way to do this is to equate the amplitude of the sinusoid to duty cycle 1. When the sinusoid goes negative, operate the other pair of the H-bridge. If the PWM frequency is too high to support ready calculation of the sinusoid in a timely manner, you can use a high-speed method such as the CORDIC algorithm in an FPGA, pipelining the hardware if you need very high frequencies of operation.
