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I am designing a board with the DRV8837 IC, which has an 8-WSON package with a thermal pad and 2 vias. When running the DRC, I am getting the following error:

Minimum Solder Mask Sliver Constraint: (0.097mm < 0.114mm) Between Via (120.867mm,7.48mm) from Top Layer to Bottom Layer And Via (121.767mm,7.48mm) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.097mm]

It's really weird, it says the sliver error is in the thermal pad, where there is no mask at all: enter image description here

This is the component in the PCB Lib, in case it's too messy to see it in the other picture with all the tracks: enter image description here

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Oh Altium my good friend. After an hour of looking at this I figured it out.

The rule is checking the sliver as if the thermal pad wasn't there, and the vias were leaving a solder mask dam: enter image description here

The distance between the solder mask openings is indeed 0.097mm as the error said. I think this situation could be handled by Altium (I'm running version 21.8.1), but, once detected, it's easily solved by making the openings smaller.

I hope this helps somebody else in the future.

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