How to avoid square wave parasitic oscillation?

Question

I try to recreate the circuit from here using discrete components logic gates. How can I avoid these parasitic oscillations in a square wave in one of its outputs?

Answer 1

Your design has the wrong threshold to act as Schmitt Triggers on slew-rate limited pulses in order to create "complementary-exclusive transitions" or a "deadtime control circuit."

The transistor delays in your simulation cause these glitches from the XOR arrangement of components.

There are many ways to correct this error.

• If the rise time is above the transistor delays, you might prevent this or make it worse

• define the hysteresis with resistor ratios. in a Schmitt trigger and input slope to exceed propagation delay. This is similar to what you have used but without the added positive feedback R's. \$V_{HT}=V+ \dfrac{R_E}{R_E+RC1}\$

• you need to specify your dead time by slew rate and thresholds then redesign according to this logic.

(from your linked earlier question)

(Design Specs are a priori is my motto then test and verify results)

suggestions

• logic diagram has excessively long connections and could be improved for readability. Compare with the example above.
• trace diagram cropped of critical time base information, show all results in future.
• it is much easier with CMOS logic.