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enter image description here

enter image description here

I try to recreate the circuit from here using discrete components logic gates. How can I avoid these parasitic oscillations in a square wave in one of its outputs?

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    \$\begingroup\$ It's not oscillation, just capacitive coupling. Set the source risetime to a more realistic value like 10 or 100ns. And 10V like the supply I guess. \$\endgroup\$ Jun 25 at 8:06
  • \$\begingroup\$ For a proper simulation of a discrete circuit with such speeds, you must include parasitic inductance of the interconnects which is in the ballpark of 10 nH and more for almost each of the interconnects. \$\endgroup\$
    – tobalt
    Jun 25 at 8:09

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Your design has the wrong threshold to act as Schmitt Triggers on slew-rate limited pulses in order to create "complementary-exclusive transitions" or a "deadtime control circuit."

The transistor delays in your simulation cause these glitches from the XOR arrangement of components.

There are many ways to correct this error.

  • If the rise time is above the transistor delays, you might prevent this or make it worse

  • define the hysteresis with resistor ratios. in a Schmitt trigger enter image description here and input slope to exceed propagation delay. This is similar to what you have used but without the added positive feedback R's. \$V_{HT}=V+ \dfrac{R_E}{R_E+RC1}\$

  • you need to specify your dead time by slew rate and thresholds then redesign according to this logic.

enter image description here (from your linked earlier question)

(Design Specs are a priori is my motto then test and verify results)

suggestions

  • logic diagram has excessively long connections and could be improved for readability. Compare with the example above.
  • trace diagram cropped of critical time base information, show all results in future.
  • it is much easier with CMOS logic.
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  • \$\begingroup\$ Hi sir, quoting from "The transistor delays in your simulation cause these glitches from the XOR arrangement of components.", does this mean that this will produce un-even deadtime between the 2 complementary waves if discrete components (discrete transistors are used) ? Thank you:) \$\endgroup\$ Jun 28 at 2:56

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