10
\$\begingroup\$

I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the forbidden case S=1, R=1 in the flip flop. Can anyone tell me what exactly is that?

By the way I have used 2-input NAND Gates to implement the flip flop. What is the difference between the NAND gate flip flop & NOR gate flip flop?

\$\endgroup\$
11
\$\begingroup\$

Assume ideal logic gates (no propagation delay) like this (image from wikipedia):

enter image description here

We know that the output of NOR gate is 1 if and only if both inputs are 0; and 0 otherwise.

When S = 1, Q = 1 and therefore \$\bar{Q} = 0\$; when R = 1, Q = 0 and \$\bar{Q} = 1\$.

But if you set both R and S to 1 we have that Q = 0 and \$\bar{Q} = 0\$ at the same time. This contradicts the relation \$Q = \bar{Q}\$. In the real world one of the gates will reach the 1 state first and the result will be unpredictable.

For the NAND-based RS flip-flop the same can be shown when R = S = 0, by writing the logic equations appropriately.

\$\endgroup\$
  • 2
    \$\begingroup\$ Why would one gate reach the 1 state in real world ? Would it still be forbidden if we don't care about the relation Q = !Q ? \$\endgroup\$ – Bilow May 8 '17 at 14:39
6
\$\begingroup\$

Asserting S means 'set the output to 1'. Asserting R means 'set the output to 0'. Telling the flop to simultaneously drive to 0 and 1 at the same time makes no sense, which is why it's forbidden.

\$\endgroup\$
1
\$\begingroup\$

Having both inputs high poses two issues:

  • The Q and /Q outputs will both be low, but downstream logic may expect that /Q will always be the opposite of Q. Depending upon the downstream logic, the fact that Q and /Q would both go low may or may not pose an actual problem, but it is something that must be borne in mind.

  • When the first input to go low does so, if the other input does not remain high until the effects of the first change have percolated through the circuit, the behavior of the circuit will not be well-defined until at least one of the inputs goes high again.

The simplest way to avoid the second problem described above is to never have both inputs go high simultaneously or for overlapping intervals.

\$\endgroup\$

protected by W5VO Mar 27 '13 at 3:25

Thank you for your interest in this question. Because it has attracted low-quality or spam answers that had to be removed, posting an answer now requires 10 reputation on this site (the association bonus does not count).

Would you like to answer one of these unanswered questions instead?

Not the answer you're looking for? Browse other questions tagged or ask your own question.