# Why is S=1, R=1 state forbidden in RS flip flop?

I have come across the RS flip flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the unstable or the forbidden case S=1, R=1 in the flip flop. Can anyone tell me what exactly is that?

By the way I have used 2-input NAND Gates to implement the flip flop. What is the difference between the NAND gate flip flop & NOR gate flip flop?

Assume ideal logic gates (no propagation delay) like this (image from wikipedia):

We know that the output of NOR gate is 1 if and only if both inputs are 0; and 0 otherwise.

When S = 1, Q = 1 and therefore $\bar{Q} = 0$; when R = 1, Q = 0 and $\bar{Q} = 1$.

But if you set both R and S to 1 we have that Q = 0 and $\bar{Q} = 0$ at the same time. This contradicts the relation $Q = \bar{Q}$. In the real world one of the gates will reach the 1 state first and the result will be unpredictable.

For the NAND-based RS flip-flop the same can be shown when R = S = 0, by writing the logic equations appropriately.

• Why would one gate reach the 1 state in real world ? Would it still be forbidden if we don't care about the relation Q = !Q ? Commented May 8, 2017 at 14:39
• Electrically, both Q and Qbar are allowed to be zero simultaneously. It violates the logical purpose of having both outputs and having them be unequal, but it's not really a contradiction as far as the NOR gates are concerned. Commented Sep 10, 2019 at 15:56
• Please can anyone help explain this, the flip flop is often times explained using the nand or nor gates, also stating that the outputs must be an inverse of each other, then I look at the And or Or flip flop with is not the case, so does that mean only nand/nor gate should be used for flip flop? 2) if any gate can be used why is the inverse always emphasised Commented Jun 16, 2022 at 16:28

Asserting S means 'set the output to 1'. Asserting R means 'set the output to 0'. Telling the flop to simultaneously drive to 0 and 1 at the same time makes no sense, which is why it's forbidden.

• By the same reasoning, deasserting R and S at the same time will tell the flip flop to simultaneously drive to 1 and 0 at the same time, which strangely does make sense for a NOR based flip flop. Commented Nov 14, 2021 at 19:48

Having both inputs high poses two issues:

• The Q and /Q outputs will both be low, but downstream logic may expect that /Q will always be the opposite of Q. Depending upon the downstream logic, the fact that Q and /Q would both go low may or may not pose an actual problem, but it is something that must be borne in mind.

• When the first input to go low does so, if the other input does not remain high until the effects of the first change have percolated through the circuit, the behavior of the circuit will not be well-defined until at least one of the inputs goes high again.

The simplest way to avoid the second problem described above is to never have both inputs go high simultaneously or for overlapping intervals.