Error (10500): VHDL syntax error at setpoint.vhd(37) near text "when"; expecting ";"

Question

It may be simple but I don`t know what's the error.

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;

-- X,Y and Z are obtained from specification (maybe even your choice)

entity SetPoint is
    Port (  
          SP_mm             : in    STD_LOGIC_VECTOR(9 downto 0);
          SP_scalingFactor  : in    STD_LOGIC_VECTOR(2 downto 0);
          RST               : in    STD_LOGIC;
          SP_error          : out   STD_LOGIC;
          SP_encoderUnits   : out   STD_LOGIC_VECTOR(15 downto 0)
); 
            
end SetPoint;

architecture yours of SetPoint is
-------------------------------------------
-- Signals and constants
-------------------------------------------
begin  

process(SP_mm, SP_scalingFactor, RST) 

begin
-------------------------------------------
-- Concurrent signal assignments
-------------------------------------------
SP_error <= '1' when RST = '0' AND unsigned(SP_mm) > 1000 else '0';
SP_encoderUnits <= STD_LOGIC_VECTOR(Shift_left("000000"&unsigned(SP_mm), to_integer(unsigned(SP_ScalingFactor))));

 

end process; 
end architecture yours;

Answer 1

when - else construct is a concurrent statement in VHDL. You cannot use it inside a procedural construct like process (). It has to be described outside process().

Update:

From VHDL-2008 std, it is supported inside process(). So either compile the code with VHDL-2008 flag or use when-else construct outside process().