It may be simple but I don`t know what's the error.

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;

-- X,Y and Z are obtained from specification (maybe even your choice)

entity SetPoint is
    Port (  
          SP_mm             : in    STD_LOGIC_VECTOR(9 downto 0);
          SP_scalingFactor  : in    STD_LOGIC_VECTOR(2 downto 0);
          RST               : in    STD_LOGIC;
          SP_error          : out   STD_LOGIC;
          SP_encoderUnits   : out   STD_LOGIC_VECTOR(15 downto 0)
end SetPoint;

architecture yours of SetPoint is
-- Signals and constants

process(SP_mm, SP_scalingFactor, RST) 

-- Concurrent signal assignments
SP_error <= '1' when RST = '0' AND unsigned(SP_mm) > 1000 else '0';
SP_encoderUnits <= STD_LOGIC_VECTOR(Shift_left("000000"&unsigned(SP_mm), to_integer(unsigned(SP_ScalingFactor))));


end process; 
end architecture yours;
  • \$\begingroup\$ Because this is valid in VHDL-2008 (and newer) but you didn't set the VHDL-2008 compiler switch. \$\endgroup\$ Jun 26 at 21:24
  • \$\begingroup\$ Did the answer below figure out your problem? \$\endgroup\$
    – Mitu Raj
    Jun 30 at 10:31

1 Answer 1


when - else construct is a concurrent statement in VHDL. You cannot use it inside a procedural construct like process (). It has to be described outside process().


From VHDL-2008 std, it is supported inside process(). So either compile the code with VHDL-2008 flag or use when-else construct outside process().

  • 3
    \$\begingroup\$ True for older VHDL revisions. \$\endgroup\$ Jun 26 at 21:24
  • \$\begingroup\$ Wasn't aware of that feature. Shall add that. \$\endgroup\$
    – Mitu Raj
    Jun 27 at 5:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.