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I am currently in training phase with verilog and I encountered an error near the 'module'. Basically what I did is that I want to assert the output q to be either '1' or '0' from my design, which is a simple D flip flop. The assertion code is written in separated file. The error are as follows:

//--------- ERROR information ------------------
Error-[SE] Syntax
Following verilog source has syntax error:
"test2a.v", 3: token is 'module'
module ^ d_ff_tb();

Below are the design module :

//--------- test2.v => design ----------------------
module d_ff (d,clk,reset,q,qb);
input d.clk,reset;
output reg q;
output qb;

assign qb = ~q;

always @(posedge clk)
begin
    if (reset)
        q <= 0;
    else
        q <= d;
end
endmodule

This is my testbench that I use to observe the design:

//------ test2a.v  ==>  testbench -----------

`include "test_sva_bind_inc.svi"

module d_ff_tb();
reg d,clk,reset;
wire q,qb;
d_ff DUT (d,clk,reset,q,qb);

initial
begin
    $vcdplusfile("dump_test.vpd");
    $vcdpluson(0,d_ff_tb);
    $vcdplusmemon(0,d_ff_tb);
    clk = 1'b0;
    forever #5 clk = ~clk;
end

task initialize;
    begin
        d = 0;
        reset = 0;
    end
endtask

task stimulus(input i, input j);
    begin 
        #12 ; d = i; reset = j;
    end
endtask

initial
begin
    initialize;
    stimulus(1,1);
    stimulus(1,0);
    stimulus(0,0);
    stimulus(1,0);
end

initial
begin
    $monitor($time, "input d = %b, reset = %b output q = %b , qb = %b", d, reset, q, qb);
end
endmodule

This is the assertion module:

//------- test_sva.svh ==> assertion module 
module d_ff_asr(input d,clk,reset,q,qb);

property UV (q);
@(posedge clk) (q||!q);
endproperty

asr_no_undeterministic_output_value : assert property (UV(q));

endmodule;

This is my "include file" :

//------- test_sva_bind_inc.svi ==> include file ------
`ifndef TEST_SVA_BIND_INC_SVI
`define TEST_SVA_BIND_INC_SVI

`include "test_sva.svh"
`include "test_sva_bind_inst.svi"

`endif

And this is my bind instance :

//------ test_sva_bind_inst.svi ==> bind instance ------
`ifndef TEST_SVA_BIND_INST_SVI
`define TEST_SVA_BIND_INST_SVI

bind d_ff d_ff_asr test_sva_inst

`endif
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  • 2
    \$\begingroup\$ This is SystemVerilog code and you have a *.v file extension. Change it to *.sv and make sure your compiler knows this is SystemVerilog code. \$\endgroup\$
    – dave_59
    Commented Jun 27, 2022 at 5:21
  • \$\begingroup\$ input d.clk should be a comma not a dot. \$\endgroup\$ Commented Jan 31, 2023 at 10:17

1 Answer 1

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I solved it already. It is quite unusual for an error to occur at the start of the module. This means that the syntax error is somewhere in the Top module / include file. In this case, the error should be in the file that I try to include in the compilation which is test_sva_bind_inst.svi . A semicolon is missing in the bind statement. The statement should be change from:

bind d_ff d_ff_asr test_sva_inst

to:

bind d_ff d_ff_asr test_sva_inst(.*);
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