Think of an op-amp's input offset voltage as being an extra voltage source in series with the one you're trying to amplify. Whatever the closed-loop gain of your amplifier, that gain will apply to the sum of your signal and this offset.
Since you wish to map the input range of 0.0V...+2.5V to an output of -5.0V...+5.0V, the relationship between input and output will be:
$$ V_{OUT} = 4 \times V_{IN} - 5V $$
The op-amp's input offset voltage is effectively a source in series with your DAC voltage source, so you can modify that relationship to include the offset as follows:
$$
\begin{aligned}
V_{OUT} &= 4 \times (V_{IN} + V_{OFS}) - 5V \\ \\
&= 4 \times V_{IN} + \overbrace{4 \times \underbrace{V_{OFS}}_{\text{in offset}} - 5V}^{\text{Total out offset}} \\ \\
\end{aligned}
$$
Your amplifier will have a gain of +4, and you should expect the input offset voltage \$V_{OFS}\$ of the op-amp to be multiplied by this value, also. For example, if your op-amp's input offset voltage is a constant -50μV, this would appear as a constant 200μV downward shift in output potential, regardless of the input.
Since you will somehow have to add -5.0V to the output, you could take the opportunity to make this (deliberate) offset adjustable, to compensate for any offset the op-amp itself is responsible for. Here's a circuit with the input/output relationship you require, with an artificially induced input offset voltage of 200μV (simulating op-amp input offset voltage, large enough to be visible on a graph, but larger than your OPx84 will exhibit):

simulate this circuit – Schematic created using CircuitLab
The actual input/output relationship of this circuit is:
$$ V_{OUT} = 4\times (V_{IN} + V_{OFS}) - 3 \times V_{ADJ} $$
You can alter \$V_{ADJ}\$ to vary the output offset, and simultaneously compensate for the op-amp's input offset voltage. I've set \$V_{ADJ} = {5 \over 3} V \$ here, with no attempt to compensate for \$V_{OFS}\$, because I want you to see the vertical shift of output due to \$V_{OFS}\$. Here are the graphs of input and output:

As you can see, each step in the output is greater than the desired value by an amount \$4 \times V_{OFS} = 4 \times 200\mu V = 800 \mu V\$.
Probably the worst problem you have to overcome is the variance of \$V_{OFS}\$ with temperature. If you knew what temperature the op-amp was to operate at, and that this temperature will not change, then \$V_{OFS}\$ will remain more or less stable and fixed over a long period of time. However, unless the device claims to have "temperature compensation" (or some other form of compensation such as chopping), no op-amp's input offset voltage remains fixed over a range of temperatures.
ADDENDUM - Input Bias Current
I feel I should also mention another source of offset which you will encounter using this OPx84 device. It has a rather high input bias current, perhaps due to it having a BJT input stage. Well, I say high, at 60nA it's not too bad, but it's huge compared to FET input devices.
Essentially that is the current that each input (inverting and non-inverting) draws, and that current has to come from whatever source is providing that input. In the case of the inverting input, the potential there is provided by R1 and R2. What the inverting input "sees" looking at that source is the Thevenin equivalent resistance, which in this case is the combined resistance of R1 and R2 if they were connected in parallel:
$$
\begin{aligned}
R_{TH} &= R_1 \parallel R_2 \\ \\
&= {{R_1 R_2} \over {R_1 + R_2}} \\ \\
&= {{30k\Omega \times 10k\Omega} \over {30k\Omega + 10k\Omega}} \\ \\
&= 7.5k\Omega
\end{aligned}
$$
While sucking 60nA out of that source, a voltage develops across that "effective" 7.5kΩ which introduces another source of offset error to the system. By Ohm's law, this additional offset will be approximately:
$$
\begin{aligned}
V_{IOFS} &= 60nA \times 7.5k\Omega \\ \\
&= 450\mu V
\end{aligned}
$$
Thankfully, the solution is simple enough; add that same source resistance in the path of the non-inverting input, too. Symmetry of the op-amp's "modified long tailed pair" input stage means that both inputs will draw roughly the same current, and by equalising the source resistance into both inputs, both inputs will suffer the same voltage offset. The net effect is a cancellation of any input offset due to input bias currents:

simulate this circuit