# What type of op-amp configuration is this from a PLL circuit?

Can someone help me to understand this attached op-amp model? We are using it in an HMC3716 PLL circuit. We don't know how it works, exactly.

Is it an integrator or a differentiator? • sorry, Correct PN: HMC3716 Jun 28 at 12:50
• 1.59pf -- those must be easy to source. Ditto exactly 603pf. Jun 28 at 14:34

It's a differential input 'broken' integrator, followed by a lowpass filter.

It follows the standard differential opamp pattern, a pair of identical input series impedances, R1x, one to each input, and then a pair of identical feedback impedances R2x + C2x, one from -In to the output, and one from +In to the output reference.

If the feedback impedances had been pure capacitors, then this would have been a differential integrator. The addition of R2x makes this a 'broken' integrator, giving it a finite constant gain and assymptotically zero phase shift above the R2C2 break frequency. Without the resistors, the phase shift would have stayed at 90 degrees at all frequencies, rendering the PLL unstable at any loop bandwidth.

It's worth noting that the R2C2 and R3C3 time constants do NOT set the loop bandwidth, that is set by the loop gain. The R2C2 time constant is set below the loop bandwidth by a factor of at least 3, similarly R3C3 must be above the loop bandwidth by at least a factor of 3. If the break frequencies come closer to the loop bandwidth, the loop stability will be affected, and the loop could oscillate. Many beginning engineers have tried to alter a PLL loop bandwidth by altering the time constants in the loop filter, and come to grief with instability.

The picture in the question is of the loop filter. It is a low pass filter, also known as an integrator.

The HMC3761 datasheet shows an example: The values are different, but the structure is the same.

The loop filter smooths the tuning voltage that goes to the VCO.

A lower cutoff frequency makes the synthesized frequency cleaner, but it also makes it take longer for the PLL to reach lock.

A higher cutoff frequency reaches lock faster, but has a noisier output from the VCO.

First, it's a differential circuit. The network formed by C1b, R1b, R2a and C2a is identical to the network formed by C1a, R1d, R2b and C2b, except that C2a is connected to the op-amp output and C2b is connected to ground. This is a canonical non-buffered differential circuit.

The presence of C1b and C1d suggests that whatever is feeding it is not of zero impedance, so I can't tell you exactly what the gain is. But the feedback network (R2a and C2a) indicate that it's an integrator with a zero at $$\\omega = \frac{1}{R_{2a} C_{2a}}\$$.

So -- it's got some low-pass to it, with C1 working against the impedance of the preceding stage, then it's a proportional-integral filter. That's pretty much a classic loop filter for a PLL.