SystemVerilog testbench giving don't care (X)

Question

Can anyone help me figure out as to why I'm getting don't cares? I think it's not reading the signaldata.txt file which is why it prints don't care.

`timescale 1ns/1ps
`include "uvm_macros.svh"

module tb_top();
    import uvm_pkg::*;
    reg clk, rst;

    //DDFS module to generate 1 MHz Sine and Cos wave 
    wire signed [15:0] sin, cos;
    wire [19:0] fcw;
    assign fcw = 20'b00000000100000110001;
    ddfs DDFS2(clk, rst, fcw, sin, cos);

    //constants
    int ADC_SAMPLE_SIZE = 65536;

    int i, I, Q, amplitude;
    //I, Q initialize to 0
    initial begin
    I = 0; 
    Q = 0;
    end

    int fd, j;                           // file descriptor and iteration variable
    int arr[65536];                      // integer array to store the 16-bit binary values

    initial begin
    j = 0;
    fd = $fopen("signaldata.txt", "r");   // signaldata.txt contains 65536 16-bit signed binary 
                                             values

    while (!$feof(fd)) begin             // loop until end of line to cover all 65536 values
    $fgets(arr[j], fd);
    j = j + 1;
    $display("%16b",arr[j]);  // I get all don't cares printed here instead of binary values
    end
    $fclose(fd);
    end

endmodule

This is what signaldata.txt looks like. There are 65536 values in total.

0000000000001100
0000000000000100
1000000000110100
1000000000010100
0000000000011100
1000000000010100
0000000000000100
1000000000110100
0000000000011100
0000000000010100
1000000000110000
0000000000010100
1000000000000100
1000000001000100
1000000000110000

Answer 1

The problem with reading the signaldata.txt file is that you are using the wrong tool for the job. You should use $readmemb instead of $fgets. $readmemb is designed to do exactly what you want: read a text file with numbers in binary format.

module tb_top;
    int arr[65536];     // integer array to store the 16-bit binary values
    initial begin
        $readmemb("signaldata.txt", arr);
        for (int i=0; i<10; i++) $display("i=%0d %b", i, arr[i]);
    end
endmodule

This is the output:

i=0 00000000000000000000000000001100
i=1 00000000000000000000000000000100
i=2 00000000000000001000000000110100
i=3 00000000000000001000000000010100
i=4 00000000000000000000000000011100
i=5 00000000000000001000000000010100
i=6 00000000000000000000000000000100
i=7 00000000000000001000000000110100
i=8 00000000000000000000000000011100
i=9 00000000000000000000000000010100