I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my design, it seems like the best solution is to use asynchronous resets, but with a reset synchronizer circuit to make the de-assert of the reset synchronous.

In this scenario, even though the flip flops are wired async, because the de-assert in synchronous, the reset is still subject to timing constraints. However, because the reset line goes to an async pin on the flip flops, my understanding is that the FPGA tools will not do a timing analysis on that signal.

My question is how do I add and define timing restrictions to the reset line so that I can verify that I'm meeting timing requirements? (And ideally have the tools optimize routing to achieve that if possible). My current design uses Libero, but I'm hoping there's a general solution that will work with Vivado and other FPGA tools as well.

  • 1
    \$\begingroup\$ Does the below response answer your question? \$\endgroup\$
    – Mitu Raj
    Jul 21, 2022 at 7:59

1 Answer 1


If you are using asynchronous reset on your FPGA design, you should add reset synchroniser for synchronous de-assertion of the reset. The reset timing paths then have to satisfy recovery and removal checks. This is more or less similar to setup and hold checks. And these checks are done only for the de-assertion of the reset.

  • If you are designing and using a reset synchronizer in RTL, you have to add a false path timing constraint on reset input, or as a better practice, add a set_max_delay timing constraint on your synchronizer data path. The delay should be constrained to minimal to place the flops in the synchronizer close to each other for better MTBF.
  • Xilinx also recommends adding ASYNC_REG attribute in the RTL of synchronizer to place the synchronizer flops together during Placement & Routing for better MTBF. Other tools may have similar flags/attributes.

That's all the basic timing constraints you need for reset timing in your design. Timing Analyzer will then perform recovery and removal checks on the reset paths and reports them.


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