1
\$\begingroup\$

I'm trying to understand a design in an evaluation board and I need some assistance.

enter image description here

In the above schematic, the PG output pin is open-drain so it requires a pull-up to VCC. I use a 100K resistor, which is how the datasheet example is done.

There is, however, an N-channel MOSFET between the source and gate. I understand that if PG is low, the VGS will be greater than its threshold voltage and the MOSFET will conduct, sinking the PWROFF_C2M_B signal.

My question is: why is this MOSFET added? Wouldn't you get the same result from just the resistor?

\$\endgroup\$
1
  • \$\begingroup\$ It looks like it's level shifting the PG signal and when VCC is not present it will disconnect PG from PWROFF. But to be sure, you need to show where the PWROFF_C2M_B goes or link to schematics that can be viewed. \$\endgroup\$
    – Justme
    Jul 4, 2022 at 18:40

1 Answer 1

1
\$\begingroup\$

Taking a 2nd look on a screen bigger than my iPod; I confirmed @PStechPaul 's feedback. TY

Reviewing the datasheet:

FEATURES: Enable (EN) and Power Good (PG) for Power Sequencing
EN Enable : Pull EN high to enable the MP8772. When floating, EN is pulled down to GND and disabled by an internal 1.2MΩ resistor.
PG Power good: open-drain output. PG changes state if UVP, OCP, OTP, or OV occurs.

The Nch FET is a common-gate Vg = high with PG driving the source, Vs with an open drain. This prevents any latchup effects to driving high any CMOS input with a Vdd lower than 0.5V below the active high. Also it can be used as a level shifter say for <= 3.3V. Instead, high is a floating drain so that the receiving chip can use it's own Vdd for pullup.

Thus the FET is non-inverting Com.Gate open-drain.

\$\endgroup\$
3
  • \$\begingroup\$ The DMN26 is an NMOS device, and the gate is connected directly to Vcc. The PG signal is connected to the source, so when it is low, the MOSFET is turned ON, so the drain essentially connects through the device to PG. This will only be necessary if the external connection has a higher voltage than can be safely handled by the PG open collector output. It does not invert the logic, and it does not provide additional current capacity, as the external load is still carried by PG. It's also possible that the schematic is in error. \$\endgroup\$
    – PStechPaul
    Jul 4, 2022 at 18:46
  • \$\begingroup\$ Revised TY @PStechPaul \$\endgroup\$ Jul 4, 2022 at 20:36
  • \$\begingroup\$ Thank you for all your valuable feedback, as its been pointed out the MOSFET's purpose is a level shifter. The PWROFF_C2M_B is connected to a power down pin which is pulled to 5V, the VCC from the MP8772 is only 3.4V. \$\endgroup\$
    – steve
    Jul 5, 2022 at 8:59

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.