# Current in a transmission line

I have a 6ft long SPI cable and I am trying to estimate the steady-state current demand on the driver. My transmission line is tuned to 100 Ω. That is, I've added a 50 Ω resistor in series with the source driver (STM32F), the cable is ~100 Ω ribbon, and the termination on the receiver side is a 330/220 combination (330 Ω going to VCC @ 3.3 V and 220 Ω going to GND).

Under testing, my oscilloscope is showing a very clean signal at the receiver with 220 mV Vpp max. swing/reflection, so I believe I have the circuit nicely tuned.

My question is: what is the current under stead-state/idle condition w.r.t. the STM32F GPIO pin?

The driver is a STM32F446 with VOL/VOH of 0.4 V (stated @ 8 mA) so I estimate about 50 Ω driver impedance, so I added the 50 Ω in series to get a 100 Ω drive impedance. The transmission line should have negligible resistance at steady state. So I estimate for HIGH logic output we have 100 Ω (source) plus 220 Ω (receiver termination to GND); so 3.3/320 = ~10 mA.

I believe the 330 Ω on the receiver termination going to VCC doesn't affect driver current in this case. For LOW logic output we have 100 Ω plus 330 Ω equals ~7.6 mA. Is my understanding correct here?

• what frequency is max? Jul 5, 2022 at 0:14
• 220mV is WAY less than what such an arrangement should be delivering. Jul 5, 2022 at 3:38
• Frequency is 4MHz Jul 5, 2022 at 13:47
• @TimWilliams I meant the overshoot/oscillation was 220mV P-P. The full signal swing was ~800mV to 3.3mV. There is also a ferrite bead at the source which reduces the dv/dT Jul 5, 2022 at 17:37
• Oh, OK. Uh, I assume you mean 3.3V there? Ferrite bead: this is important information, relevant to the signal path; consider adding it to your schematic. An FB serves as source termination, at frequencies where its resistance is significant; for short-ish cables like this, a FB alone can do the job for signal quality purposes. Jul 5, 2022 at 23:50

what is the current under stead-state/idle condition w.r.t. the STM32F GPIO pin?

The max current is 402 mV over the 50 ohm added source R or 10.2mA

Your calculations are incorrect but with the same result by coincidence.

The current is measured by the voltage change across the source matching R and for the load using Thevenin's Theorem with KVL.

Since Vdd and Vss = 0 Ohms the resistor divider impedance is in parallel.

R1//R2= 132 Ohms, 2.0V = 220/(220+330) * 5V This added to the 100 ohm source for the loop current.

Since 132 Ohms does not match the 100 ohm cable some positive waves are reflected back. This creates some small excess current at the source at is only slightly more than 50% of the rating.

The current From the datasheet, there are tolerances:

"Most GPIO ports an sink or source up to +/-20 mA (with a relaxed Vol,Voh) except PC13, PC14 and PC15... +/-3mA. "

@ Io = 20 mA
Vol = 1.3 V max low
Voh = VDD - 1.3 V min high


This implies the CMOS FET RdsOn output impedance = 1.3 V / 20 mA 65 ohm max. Nominal is 50 Ohms = 0.4/8mA The minimum impedance will likely be 33 Ohms.

The interesting thing about matching the source but not the load is that the reflections are one way, so the source has overshoot from the load being higher than the 6ft cable, while the load sees the incident wave attenuated without reflections.

The transmission line was set to 100 Ohms 2.7m

## Correction

(senior's moment) 3.3V termination

• Sim link much appreciated! Lot's of new info to devour but I'm beginning to understand now. I was able to play with that, convert to AC termination and get rid of the bias. AC Thevenin Termination Sim Jul 5, 2022 at 18:32

No, not correct. The 330 ohms pull high and 220 ohms pull low. So termination impedance is 132 ohms, into 1.32 volts.

So if driver pulls to 3.3V or 0.0V with 100 ohm source impedance, you can calculate the currents.

Another way to think this is that there is the 330 ohm and 220 ohm termination network, and the source impedance of 100 ohms is either in parallel with the 330 ohms or the 220 ohms.

Now another questions could be asked, if or why a 6ft SPI bus at logic levels makes sense (it might) or if DC loading is an issue, why use DC termination instead of AC termination.

Depending on the receiver, the voltage may not be high enough for it to see a valid logic high level.

• @TonyStewartEE75 I think you used 5V while the termination VCC is 3.3V in the post. 3.3×220/550 is 1.35. Jul 5, 2022 at 4:59
• I couldn't figure out how the 132ohm was determined by the R1||R2 combo Rt = R1*R2/(R1+R2). I didnt even know what I was using was called "Thevenin Trace Termination" until I found this interfacebus.com page. Jul 5, 2022 at 17:29
• Also I didn't notice until after my post that my termination is adding 800mA bias to the low side which is a bit close to the 1.1v VLH. I played with @TonyStewartEE75 falstad sim and switched to AC thevenin termination using 3pF caps and tuned resistors to Zo = 100ohm and it looks even better. Jul 5, 2022 at 17:33