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I am planning to do a 0.3 mm dia via array under the exposed pad of a SMD component. 0.3 mm so that the via is small enough that solder mask covers most of vias in the bottom layer so that solder wicking doesn't happen from top layer to bottom layer.

When considering the heat transfer from top layer to bottom layer would there be any difference in using a 1 ounce vs 2 ounce PCB? Let's say we consider unfilled vias with 1.6 mm board thickness.

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    \$\begingroup\$ I'm not sure but IIRC the via plating thickness doesn't change with external or internal copper layer thickness. You should consult your PCB manufacturer. \$\endgroup\$
    – Rohat Kılıç
    Commented Jul 6, 2022 at 13:34
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    \$\begingroup\$ So, three things: first is your question is an "XY" question (xyproblem.info) please tell us what you are really trying to do; second, your PCB specification doesn't include enough data to actually answer your question, who is MFG your PCB and what is the actual stackup you're using? Is your board 1.6mm thick (62mil)? Thicker? Thinner?? Third, the Via plating thickness matters too, or you can have them filled, or plugged... \$\endgroup\$
    – pgvoorhees
    Commented Jul 6, 2022 at 13:38
  • \$\begingroup\$ Since we have not decided on a manufacturer, I am asking in general PCB manufacturing process for a particular thickness for unfilled vias. What I am trying to gauge is will there be a difference in thermal conductivity from top layer to bottom with difference in copper thickness of the PCB. \$\endgroup\$
    – EarthLord
    Commented Jul 6, 2022 at 13:42
  • \$\begingroup\$ My response is a terrible answer because of the lack of information: Yes, there will be a difference, all things being equal, it will be worse because of the increased thermal resistance due to a larger cross sectional area of the copper layer. Please tell us what you are trying to do if you want a better answer. \$\endgroup\$
    – pgvoorhees
    Commented Jul 6, 2022 at 13:50
  • \$\begingroup\$ Be careful with stop mask over thermal vias. Once we had the problem that the solder mask wicked through and formed a lacquer blob on the thermal pad on the component side which made the boards nearly unusable (component did not sit flat). Our vias had 0.3 mm final opening, so in some cases this can cause trouble the other way round. In the end we did not cover those thermal vias any more. Maybe it is safe for some board houses. Otherwise smaller and more vias could prevent this. \$\endgroup\$
    – datenheim
    Commented Jan 4, 2023 at 19:59

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It looks like the via wall thickness remains the same when its a 1 ounce vs 2 ounce copper PCB with some manufacturers. Both JLC PCB and PCB Way confirmed that the wall thickness remains 18um for 1 ounce and 2 ounce PCB. With this it looks like the thermal resistance of the via remains the same.

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  • \$\begingroup\$ I got the same confirmation from two very different board houses. Someone mentioned that few board houses may offer increased plating thickness for vias, but I can give this feature no specific name so far. \$\endgroup\$
    – datenheim
    Commented Jan 4, 2023 at 20:02
  • \$\begingroup\$ The via plating stays the same, but with an increasing hole diameter, the thermal resistance changes to the better. \$\endgroup\$
    – RemyHx
    Commented Jan 4, 2023 at 21:54
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When considering the heat transfer from top layer to bottom layer would there be any difference in using a 1 ounce vs 2 ounce PCB? Let's say we consider unfilled vias with 1.6 mm board thickness.

Not that I know of, it's the via plating thickness that determines how much copper you get on the wall of the vias. Usually the best way to find these numbers is ask the PCB manufacturer what they do for their default thickness. You can also specific what kind of via plating thickness you need and include it in the fab file. AFAIK this is the same for all vias on the board with standard processes.

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