In I2C protocol one data bit is transferred during each clock pulse of the SCL. All the SCL-SDA timing diagrams I've encountered so far are shown as below:
My problem is that instead of one bit of data is sent following a clock rising edge, above we see that the clock rising edge comes after one bit of data. If we look at the very left for instance, we see that MSB is created before the clock.
This makes me super confused, since the clock supposed to be used to sync the data bit transfer yet in this case it seems it lags the data. Can someone clarify the relationship between clock and data bits?
Here another example where, again, the data bit occurs before the clock: