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I am designing my first 4-layer PCB and I have a question related to the plane on the bottom of the board.

At this moment, my plane stack-up is :

  1. Signal traces + ground fill
  2. Ground plane, no traces
  3. 5 V plane, no traces
  4. Signal traces + ground fill

The board contains a few different voltages, but except for the 5 V connected to almost every part, they are generated and used in localised area. I was then wondering if I could use the bottom copper to define multiple power planes around where they are used and created. They could also act as thermal dissipator.

However, I do not know if it is recommanded or not, and if it can cause some unwanted effects. My circuit does not have high frequencies components except for a few components using 10 MHz signals.

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4 Answers 4

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I was then wondering if I could use the bottom copper to define multiple power planes around where they are used and created. They could also act as thermal dissipater.

I don't see why not. This is pretty much normal practice for PCBs. You could even use the top layer for localized power planes if you wished. With some care you could probably use layer 3 for some localized power planes if heat-sinking wasn't needed on them.

Keep the 0 volts ground plane as intact as you can. That's a rule that may be broken if you are experienced in PCB design and circuit analysis.

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It's fine. I use signal/gnd/-15/+15 stack up for opamps. It's amazing how much signal you can route on top layer when those pesky criss crossing dual supplies are out of the way.

Note the +5 plane on L3 will couple slightly with the small power pours on L4 because parallel layers are capacitors. So if your+5 is noisy it's better to put the copper pour with the low noise voltage reference on top of the ground plane. But if you don't have low noise stuff, no issues.

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As others notices, it's a good idea. What you get by having say a ground plane on more than one layer - even if it's a partial plane - is a reduction in effective impedance of the ground plane. To get this benefit, there must be plenty of stitching vias between the primary plane on layer 2 and "vestigial" planes on other layers. Same goes for power: if you double the local power plane on two layers and stitch them well with vias, you get half the impedance.

If the product can afford buried vias then it's possible to get this without taking up board space on other layers. But this matters only in very high density designs where all the components are almost touching each other and there's no "empty space" left on the outer layer(s).

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  • \$\begingroup\$ Not seeing how this answers the question? \$\endgroup\$ Jul 9, 2022 at 4:19
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Your board is more like

  1. Signal traces + ground fill

  2. Ground plane, no traces

    CORE

  3. 5 V plane, no traces

  4. Signal traces + ground fill

The 5V in Layer3 will couple its return entirely to GND in Layer4. Make sure when you pour multiple power (none 5V) in Layer4, you don't cut off the 5V return path completely.

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