# PLL phase frequency detector

If there is a constant phase difference between the VCO signal and reference signal, the phase frequency detector will always givr an error signal. How can the PLL lock in this condition?

I mean the VCO can only change its frequency and there is no parameter in a VCO for phase change.

Changing frequency in this condition will never lock the PLL.

Am I missing something?

• The question lacks detail, but I’ll try to help. A PLL will only link when the frequency is correct and the phase is correct (what counts as ‘correct’ depends on the design and configuration of the device) so if the frequency is correct but the phase is incorrect the PLL will allow itself to drift slightly until the phase is correct. Does that help?
– Frog
Jul 9, 2022 at 3:07
• yes , thank you 😊 , Jul 9, 2022 at 3:20
• but how pll drift to adapt the phase ? I know block diagram of pll and I didn't see that option ? Jul 9, 2022 at 3:21
• @frog I didn't see this option in any pll diagram, Jul 9, 2022 at 3:35
• simply because nothing is ‘locking’ the PLL, it will never perfectly match the desired frequency while it’s not locked, so will eventually drift one way or the other
– Frog
Jul 9, 2022 at 6:00

Understand the relationship between phase and frequency.

If you have two signals of slightly different frequency, the phase is forever rotating between them.

Say the signal edges line up at t=0. And say they are 1kHz and 1.01kHz.
After 1ms (1 cycle), the 1.01kHz signal will be leading by (1 - 1.01) / (1) = 1%, or 3.6°.
After 10ms, it will be leading by 36°.
After 100ms, it will be leading by 356.4°.
After 101ms, the edges coincide again, and the process repeats.

Phase is adjusted simply by nudging the VCO up and down a little bit. Mathematically, we say that phase is the integral of frequency difference. Using a control loop to force that integral to zero, doesn't just ensure the frequencies match closely -- it's a perfect integrator* by definition, so if it's locked at all, the frequency must be exact!

*Unlike an op-amp voltage integrator for example, which still has finite gain at DC.

When in a nearly locked condition , a PLL changes the oscillator frequency slightly when a phase difference is detected. This means that the frequency will become only stationary if the phase is matched.

$$\frac{df}{dt}\propto\Delta \phi$$

You’re missing a key relationship between the phase and frequency:

Frequency is the rate (time derivative) of phase change.

Conversely,

Phase is the time integral of frequency.

You change one, you always affect the other. By changing the VCO frequency, you can get any frequency at any phase you need. That’s from basic theorems in calculus.

Both involve a constant scaling factor (multiplier). The multiplier is 1 for angular frequency. For frequency in Hz, it $$\1/(2\pi)\$$ for frequency derived from phase change rate, and $$\2\pi\$$ for phase derived from integral of frequency in Hz.

The error voltage from the phase detector goes through a low-pass filter to the voltage-controlled oscillator. The oscillator frequency varies according to the error voltage, and "settles down" to zero frequency and zero phase error, as defined by the design of the phase detector. Some PD designs go for zero phase error, some go for 90 degree offset. The key is that the PD output voltage is what controls the VCO frequency, and hence the phase offset.