Understanding MOSFET forward-bias safe operating area

Question

I am planning to use some power MOSFETS as simple on/off switches for a high voltage battery discharge circuit I'm designing. The circuit will consist of several parallel resistors of relatively high resistance. I want to be able to switch off individual rungs of the ladder in order to add or remove parallel resistance paths to manipulate the overall resistance of the circuit. It will look sort of like this.

^{simulate this circuit – Schematic created using CircuitLab}

I know I haven't shown how I'll drive the gates of the MOSFETs, I left that out of this schematic for simplicity's sake because I have that part of the equation well figured out. R1, R2, and R3 will actually be comprised of multiple 100w resistors in series. Heat dissipation has been considered! Once again, they're represented this way schematically for simplicity.

M4 is supposed to be a master on/off for the circuit. It's sort of redundant given the circuit breaker, but it's easier to automate voltage to a gate than physically throwing a breaker- and the whole purpose of this design is automation.

Also, I'm not really sure if the 300k ohm resistor is necessary, but in my head the idea is to allow a very small current through the circuit when the MOSFETS are turned off, which should mean that if I throw the circuit breaker switch to OFF that the circuit will bleed off any residual charge into the negative terminal of the battery. Correct me if that is wrong or unnecessary or I should go about it in a different way.

I believe I have properly sized the MOSFETS I want to use, but I've run across the following graph in a data sheet that I somehow overlooked before. At first glance I thought it disqualified the MOSFET I'm looking at, but I think I was misinterpreting. Here is the digikey page for the actual FET in question and here is the graph I'm a bit puzzled by:

Now here is how I think I can interpret this:

If, for instance, M1 and M4 are both ON given R1's resistance the current through each FET should be about 240 mA. And if I look at the graph above, it would seem that at 240v that 240mA is beyond the Safe Operating Limit for continuous DC.

Except the Vds isn't actually 240 when the M1 is ON, it is actually basically zero since R1 drops almost all of the voltage. So both M1 and M4 are going to be seeing decent current but at very low Vds. In other words, they'll be operating in the safe region.

When M1, M2, and/or M3 are ON but M4 is OFF, R1, R2, and/or R3 won't drop the voltage, so the Vds of M1, M2 and M3 will indeed be 240v, however the current will be near zero. In other words, they'll be operating in the safe region.

Is this correct? Do I have it right?

If I do have it right, it would seem that the only time this would be an issue is if I were to, say, swap the positions of M4 and the Circuit Breaker. If I did that, there would be no resistive load to drop the voltage before the FET, so Vds would actually be 240v and current would be the same, moving things outside of the Safe Operating Area.

Perhaps this is exactly what the term "Forward-Bias" means in this context. I admit to not fully understanding the term as applied here.

Answer 1

The FET doesn't switch instantaneously. The "OFF" point (I=0, V=Max) has zero dissipation, and the "ON" point (I=Max,V=0) has low dissipation. When switching, both I and V will go around on a trajectory that you can plot, for example using the simulator. At each point where V and I are not zero, there is a non-zero instantaneous dissipation V*I, and somewhere along the line there is a dissipation peak.

The SOA graph has V and I as axes, and lines labeled with time. So if your MOSFET is going to spend 1 second at 100V AND 1A, which means 100W, this would be point "A" (red). This is quite far to the right of the "1 second" line, which means it will absolutely blow up. However, 100V and 0.4A (point B) is survivable for one second (note Tc=25°C means this will only happen if the MOSFET is well cooled, and "single pulse" means it has to cool down before doing it again).

The point C "high voltage and zero amps" is not on the graph, because zero doesn't fit on the log scale. But it's as good as there, and this is in the "DC" zone, which means an unlimited amount of time. Same thing for point D, the MOSFET being ON with little voltage and some current. Note this one depends more on the heat sink than the other, because it will dissipate RdsON x I^2.

In fact, you can plot the entire curve of I,V during the switching event.

The red and blue lines simply represent I and V varying together as it switches. The problem with this plot is it doesn't say how long it stays at each point, but that will do.

If the load was inductive, that would be the blue line, current stays rather constant until the FET switches fully. For a resistive load, current will vary more smoothly, so the peak dissipation is lower.

On the graph that the I/V trajectory doesn't even cross the DC line. So if you switch it at a reasonable speed, say 100µs, to make sure it doesn't make EMI, it's going to spend less than a few tens of µs at a peak dissipation that it would be able to tolerate for an unlimited amount of time with a proper heat sink.

Basically, this means your MOSFET is way too chunky, which is bad if you want to save 50 cents on the cost. But if it's a prototype, then it's nice, because it means the FET won't blow due to SOA.

If switching frequency is high (for example you try to PWM the resistors) and it switches too slowly, then cumulative switching losses may overheat it. So if you plan to PWM it, you got to put numbers on the switching losses. If you don't plan to, no need to bother.

Now...

The wires at (1) are probably a mistake if you want to control each resistor.

When all FETs are off, the potential of point 2 is not known. It depends on leakage through M1-3. That could raise the voltage on their sources quite a bit. If one of M1-3 is turned on while M4 is off, then the voltage at point 2 will rise to 240V.

This could be a problem for the drivers. The whole point of low-side FETs is they're simple to drive, but in this case, you can't use low-side drivers for M1-3.

Another thing is the resistors. If they are big wirewounds, they'll have some inductance. A flywheel diode across them could be a good idea. It depends on the inductance and the switching time.

Answer 2

Your first question has to do with M1 and M4 conducting. Because they both have \$550 \text{ m}\Omega \$ resistance, a little over \$1\text{ }\Omega\$ in all, they will drop so little voltage that they both will be operating well within the safe zone.

Your second question has to do with M4 not conducting, which means that M1, M2, and M3 also will not be conducting. There will be current through R4, though, and it will drop nearly all of the 240 V. This will expose M4 to this voltage, but without any current. The datasheet says the device can tolerate 650 V in the off state, so this still is in the safe operating region.

Your third question has to do with interchanging the circuit breaker and M4. If there is no conduction, the 650 V tolerance still is ample. With conduction, the resistors still drop nearly all the voltage, so the transistors remain in the safe operating zone.

Your transistors are chosen well: they withstand the off-voltage and they tolerate the on-current. Using the bleed resistor incurs a small loss of efficiency during normal operation, but is fine for removing charge once the circuit breaker is open.

There is an issue associating with swapping the positions of M4 and the circuit breaker: the gate will need to be high relative to its source voltage. This is feasible with a voltage shifter, but generally inconvenient.