The setup

I'm currently doing some experimentation with 3-phase inverters for BLDC motors and current sense. I have at hand this board featuring:

  • IR2103 MOSFET driver. LIN# inputs are connected to HIN inputs through jumpers
  • 5 mohm shunt resistor
  • LMV324 Op-Amp for low-side current measurement, in non-inverting configuration, Gain=25

The setup comprises of:

  • STM32 NUCLEO F411RE providing to the inverter 3 HIN inputs and 3.3V VCC (for Op-Amp)
  • 24V power supply for PVDD
  • 3 27 ohm resistors connected at the motor terminals in Y configuration, to "simulate" a 3-phase load.

In the code, I'm generating 3 left-aligned PWM signals (frequency=25 kHz) for a-b-c terminals with duty cycles of, respectively, 30%, 50%, 80%.

With an oscilloscope I'm monitoring the 3 "motor" terminals and the IS1, IS2, IS3 terminals (the amplified voltage across the low-side shunt resistors on the 3 branches)

What I expect to see

  1. 3 0-24 V square waves with duty cycles of, respectively, 30%, 50%, 80%.

  2. The IS1 (Ia) current-sense voltage:

    • 0V for the first 30% of the cycle, since all high-side mosfets are ON (and low-side ones are OFF)
    • some voltage corresponding to ib+ic = -ia (theoretically around 592 mA) for the following 20% of the cycle, since the low-side MOSFET on branch a is ON while on the other 2 branches the high-side is ON
    • some voltage corresponding to -ia = ic/2 (theoretically around 296 mA) for the following 30% of the cycle, since only the c high-side MOSFET is ON
    • 0V for the rest of the period, since all low-side switches are ON
  3. The IS2 (Ib) current-sense voltage:

    • 0V for the first 50% of the PWM period since b low-side is always OFF
    • some voltage corresponding to -ib = ic/2 (theoretically around 296 mA) for the following 30% of the cycle
    • 0V for the rest of the period
  4. The IS3 (Ic) current-sense voltage always 0V (all low-side MOSFETS ON, no current circulation)

I simulated the approximated circuit with the Falstad circuit simulator, obtaining the following results, which seem to agree with the above analysis (currents Ia, Ib, Ic are currents flowing from the low-side MOSFETs' source to ground): Falstad results

What I actually see

The voltages at "motor" terminal appear to be correct: 0-24 V square waves with the correct duty cycles:

Voltages at motor terminals

What I cannot understand is the output of the current-sensing amplifiers:

Voltage at terminal a and sense voltages

Where the first signal is the voltage at terminal "a" (for reference with the previous image, used also for triggering) and the following 3 signals are the Is1, Is2, Is3 current sense output voltages.

I understand that for a current of 592 mA I should get an amplified voltage of:

Vs = Gain * Rsense * I = 25 * 0.005 * 0.592 = 0.074V

which is maybe hardly detectable on the oscilloscope, but I cannot understand the big transient at the beginning of the PWM cycle, with its long-lasting settling tail. Wouldn't this invalidate any ADC readings performed on these signals in order to implement current control (field oriented control)?

So the question is, what am I looking at? Is the previous analysis wrong? Is there some hardware problem with the Op-Amp or the board in general?


Adding a clarification: at this stage I'm not controlling a motor or doing some meaningful switching patterns: the load at "motor terminals" is just 3 resistors in Y configuration. I'm just experimenting with the current sensing circuitry, applying a known PWM pattern (maybe not meaningful for proper motor control) and checking if the signals are coherent with what I expected.


I add some more waveforms after some comments regarding the possibility of shoot-through. These are the signals related with turn-on and turn-off of leg "a" of the inverter, output of IR2103. From top to bottom, first is HO, second is Vs ("motor" terminal), third is LO.

Turn on leg "a" Turn off leg "a"

With some difficulties I was also able to probe the current sense resistor, whose voltage is the fourth signal in the following image: Current sense probing

  • \$\begingroup\$ Please share your layout and schematic. I have done low side current measurement many times and it is way harder than it looks, since the discharge of Cds together with a small shunt can trigger the impuls response of the current amplifier, which looks pretty much as in your graphs. Do you have some differential and common mode filters inline with the amplifier inputs? \$\endgroup\$ Jul 9, 2022 at 18:38
  • \$\begingroup\$ Thank you for your comment, unfortunately I cannot share the layout because I don't have it, but the schematic is linked in the question (here). In the same github repo that is linked there are some photos of the board as well, if that can help. Anyway no, there are no filters, the shunt voltage is fed directly to the non-inverting input and amplified with 1K/24K resistors. Shunt resistor is 5 mohm. \$\endgroup\$ Jul 9, 2022 at 18:50
  • \$\begingroup\$ Did you estimate your power budget as a problem? \$\endgroup\$ Jul 9, 2022 at 18:52

3 Answers 3


The output capacitance (drain / source) of the low side MOSTFETs must be charged when the high side FETs turn on. So you can expect a short voltage peak across the shunt resistors.

The LM324 is a bit slow and integrates this peak internally. The limited slew rate and the feedback loop response via 24 kohm together with the input capacitance is not that fast either. This creates a large overshoot at the OpAmp output.

You can ignore that and sample the current after the settling time or use a much faster OpAmp. A low pass R/C filter between the shunt resistors and the IN+ inputs of the OpAmps stretches and attenuates this voltage peak in a way, that the LM324 may can follow. However, a delay before the current measurement can be taken, is needed as well.

  • \$\begingroup\$ Yes, that is exactly the behaviour we can see here. I had similar issues some time ago, the only way to tackle this problem is to use a differential and common mode filter for the opamp. Try a Rs <=10 ohm with caps of something in between 10nF-100nF \$\endgroup\$ Jul 9, 2022 at 18:43

It looks to me as though the bootstrap capacitors are discharging faster than the switching rate can recharge them. One option is to increase them by, say, a factor of 10 and see whether my inference is correct. This should keep the bootstrap capacitor charged for long enough to operate the high sides throughout a switching period.

A bigger problem is with the waveform itself. Without knowing what you motor really wants to see, I'm surprised. I would have expect two high sides to be on and one low side also to be on, with the particular combination switching like this: ABc aBC AbC and repeating. Perhaps what you're doing is correct, but it is not obviously correct.

  • \$\begingroup\$ I have some electrolytic 100uF, or some ceramic 4.7uF cap lying around, I might try and substitute. What if I modify the switching frequency instead? Could that achieve the same result? If the bootstrapping wasn't working properly (high sides not ON for the correct amount of time), shouldn't this affect the voltage waveforms? They appear correct to me (first oscilloscope image) \$\endgroup\$ Jul 9, 2022 at 16:14
  • \$\begingroup\$ Sometimes electrolytic capacitors don't respond well to fast switching operations, although ceramic capacitors tend to be quite good. You could try either. Or you can increase the frequency, which means that the bootstrap capacitor gets recharged more frequently and doesn't need to provide power for as long an interval. \$\endgroup\$ Jul 9, 2022 at 16:25
  • 1
    \$\begingroup\$ There is nothing wrong with the bootstrap capacitors. The output voltages are stable during the on time period. The waveform is a test pattern, not a useful motor drive signal. \$\endgroup\$
    – Jens
    Jul 9, 2022 at 17:19

Your board looks fine.

The setup comprises of: STM32 NUCLEO F411RE providing to the inverter 3 HIN inputs and 3.3V VCC (for Op-Amp)

IR2103 needs to be told when to turn on each FET separately. So it has one input signal per FET, total 6 inputs signals for your three phase bridge.

So you must generate the 6 signals with your micro and insert some dead time to make sure the top FET and the bottom FET of the same leg of your bridge do not turn on at the same time, which would short the power supply and cause a huge current to flow.

It looks like your micro is only sending 3 signals and not 6, so I guess you do have some cross-conduction, a huge current spike does flow, and the current sense opamps just do their job and report it.

This will heat your MOSFETs unreasonably, so an investigation is in order.

If you want a driver chip that will insert the dead time automatically, so it needs only one PWM signal to drive both FETs, OnSemi has a whole family of drivers like that. Check ADP3120, but there are many more recent ones.

  • \$\begingroup\$ The micro is indeed generating only 3 PWM signals, connected to the HIN inputs of IR2103. The same signals are routed (via jumpers on the board) to the LIN inputs of the IR2103. According to my understanding of the datasheet, if the 2 signals are in sync (figure 1 in the datasheet you posted) the HO/LO switching should be correct anyway. Moreover, doesn't the IR2103 insert some dead-time by itself to prevent shoot-through? (typ. 500ns from datasheet). Anyway since the board allows also for 6 independent PWM inputs (removing the jumpers) I will try this solution and see if it helps \$\endgroup\$ Jul 9, 2022 at 18:01
  • \$\begingroup\$ My bad! You're right, it's supposed to do that. Now, that's really weird. Can you probe the +12V rail, the high voltage supply, and the current sense resistors themselves when it misbehaves? \$\endgroup\$
    – bobflux
    Jul 9, 2022 at 18:19
  • \$\begingroup\$ I added some more signal captures to my original question. What I would like to ensure is that the switching is ok (no shoot-through) and that the problem only resides in the current sensing op-amp \$\endgroup\$ Jul 10, 2022 at 11:59
  • \$\begingroup\$ It looks OK, I don't see any sign of cross conduction and the driver switches the MOSFETs in the proper order... In fact, the noisy trace you measured on the sense resistor looks pretty good. So it could be the opamp. I looked at the github schematic, there's one problem: the unused opamp has floating inputs. Normally the unused opamp is wired as a follower with a suitable input voltage like 0V, to make sure the inputs don't pick up noise and disturb the other opamps in the package. \$\endgroup\$
    – bobflux
    Jul 10, 2022 at 20:37
  • \$\begingroup\$ Another problem is lack of decoupling and also probably layout. Can you post a pic of the board (both sides) ? \$\endgroup\$
    – bobflux
    Jul 10, 2022 at 20:39

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