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An old circuit I'm checking was built using a philips 74HC273 (CMOS dev) datasheet in a card that is receiving reset and other signals from another card. In that other card, reset signal comes from a 245 3-state non inverting buffer datasheet (biCMOS dev). This buffer brings a signal from a microcontroller output gpio to an input pin buffer. When buffer is enabled (by another microncontroller output) the signal pass from port A to port B. The second card takes this buffered signal (through connectors) and brings it to the 74HC273 device MR (master reset) input pin. They both devices are powered by 5V.

This flip flop should be kept reset from power on, for propper system operation. This means to avoid the effect of unkown transitional states of the control/data flip flop signals. Problem is during power on transition, while mcu is starting. Power on is quick in comparison with mcu setup process, so when FW put a reset activation on the reset pin.

As the printed circuits are long time ago built and connected to the system, I'm first doing some improvements that are easy to carry out. As in example; to add a pull down resistor between connector pins.

schematic

simulate this circuit – Schematic created using CircuitLab

I know the usual resistor values could be from 4.7K to 10K according to cmos technollogy due input internal impedance, source and sink current, etc.. But I would like do some theorical calculation. I would like to mathematically get a real min and max resistor values, hence, to be more accurate.

I was following and reading some guides about this points. Some of them, like this one: web source about R pull up/down calculation are explaining how they arrived to get these expressions:

  • Rpull-up = (Vsupply – VH(min)) / Isink --> Where Vsupply is the supply voltage, VH(min) is minimum accepted voltage as High, and Isink is the maximum current sinked by the digital pin.
  • Rpull-up = (VL(max) – 0) / Isource --> Where (VL(max) the maximum voltage is accepted as logic Low, and Isource is the maximum current sourced by the digital pin.

Some other documents I found were taking into account the parasitic input capacitance of input pins too. Specially if this one could be enough capacitance value to affect the RC rise time, as a parameter for limiting Resistor value.

My two questions:

1.- I haven't found the "I source/sink" parameters on this datasheet. As well as I have often seen I sink/source at microcontrollers datasheets I haven't seen this specifyc information here. So I'm unable to use this value to put at any of the previous expressions.

2.- I'm not completely sure about how the pull down resistor will playing at the input with its Cin, as Cin is allocated between pin and GND at pull up configuration, having connected to it a serial R attached to VCC, and now I'm having Cin + R attached to GND. In this pull down configuration is this R affecting the rise/down time?

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    \$\begingroup\$ Just to be sure, you have 74ABT245 as output, and 74HC273 as input? So different logic families? And what supply voltages they are powered from, both with 5V +/- 5%? \$\endgroup\$
    – Justme
    Commented Jul 11, 2022 at 17:21
  • \$\begingroup\$ Yes, 245 is the output and 273 is the input, 245 put the reset into MR (flip flop master reset) pin. \$\endgroup\$
    – Suvi_Eu
    Commented Jul 12, 2022 at 6:09
  • \$\begingroup\$ I know the first device is biCmos, and the second one is Cmos. I was thinking about this. The combination seems to work well (even I built this part of the circuit on a protoboard and no problem with logic level interpretation is noticed). They both are powered by 5V. Problem is during setup transition, while mcu is starting. Setup is quick in comparison with mcu starting process, when FW put a reset activation on the reset pin. I would not put the reset into the 3state buffer, but cards are designed and produced 12 years ago. \$\endgroup\$
    – Suvi_Eu
    Commented Jul 12, 2022 at 6:12

2 Answers 2

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That is a difficult situation.

The output chip logic family type is ABT while input chip logic family type is HC.

Basically a TTL output is connected to a CMOS input, and while it may work most of the time being directly connected in real life, it would be a concern to anyone that has looked at the datasheets for actual specifications.

The HC chip data sheet says that under recommended conditions, the logic input voltage must be at least 3.15V or higher, albeit that is rated at 4.5V supply, so at 5V supply, it should typically approximate to be at least 3.5V.

The ABT chip is only guaranteed to output 3.0V under load, and typically only 3.4V under load, but that's when there is the rated 3mA load on output. So unloaded output could be higher, but very near the required 3.5V, barely above it, because it is not guaranteed.

The problem is if you want to add more load to the ABT output in the form of a pull-down resistor.

The loaded ABT output voltage could easily drop below recommended HC input voltage.

Which is why normally ABT output to a HC input would actuall have a pull-up reistor for improving compatibility.

Putting a pull-down will only reduce compatibility and may give you more problems, and the problems may already originate from the designed circuit, if the original desiner did not understand how to interface between different logic level families properly.

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  • \$\begingroup\$ Being fair this pull up resistor was there. But this pull up is keeping MR pin high during power on and we need to see here a logic '0' while mcu is starting. So the pull up resistor was forcing the opposite needed level. This is why I was thinking the way to force a logic '0' here (with a pull down), where the picture is showing. \$\endgroup\$
    – Suvi_Eu
    Commented Jul 12, 2022 at 10:25
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  1. The datasheet does not bother to differentiate between source and sink, and has only the input leakage current, II. ("Leakage" because the MOSFET gate is isolated from the channel, and you see only what leaks through the gate isolation and through the ESD protection circuits.)

  2. It does not matter whether you assume CI is connected to VCC or GND; for high-frequency signals, they are the same. In general, the input capacitance is small enough so that you can disregard it.
    When you have a pull-up or -down resistor, and when the line is not actively driven otherwise, then the capacitance is (dis)charged only through the resistor. This affects the rising edge for a pull-up, and the falling edge for a pull-down. (When the '245 is active, both edges are fast.)

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  • \$\begingroup\$ Yes it is, datasheet shows only the I leakege. But should I consider the ILeak as a source/sink current for my resistor calculation? How can I get this R value? I would like to compare the theorical solution versus the observations I made: 5K solves floating situation, but it doesn't for device normal operation state, 10K solves floating and device normal operation state too. I would like to get calculation and compare both lab and paper results.. \$\endgroup\$
    – Suvi_Eu
    Commented Jul 12, 2022 at 10:33

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