# NMOS level 8 Ltspice model of 2SK4177

After downloading a model from https://www.onsemi.com/design/resources/technical-documentation?rpn=2SK4177, I deleted everything apart from what was between .MODEL and ), so I ended up with a xxx.txt file containing this:

.MODEL 2SK4177 NMOS (                                LEVEL    = 8
+VERSION  = 3.2            TNOM     = 27             TOX      = 1.0E-07
+VTH0     = 2.70           K1       = 3.86           K2       = -0.04
+NLX      = 4.70E-07       DVT0     = 3.12           DVT1     = 0.09
+DVT2     = -0.01          U0       = 600            UA       = 1.04E-10
+UB       = 1.00E-21       VSAT     = 1.84E06        A0       = 0.66
+AGS      = 1.00           A1       = 0              A2       = 1
+RDSW     = 9.00E05        PRWG     = 0.0E00         WR       = 0.92
+WINT     = 0              LINT     = -7.20E-08      VOFF     = 0.00
+NFACTOR  = 0.64           CIT      = 0              CDSC     = 2.40E-04
+CDSCD    = 0              ETA0     = 0.14           DSUB     = 0.96
+PCLM     = 0.01           PDIBLC1  = 0.10           PDIBLC2  = 1.20E-03
+DROUT    = 0.96           PSCBE1   = 1.00E11        PSCBE2   = 1.00E-05
+PVAG     = 0.01           DELTA    = 0.03           NGATE    = 1.0E19
+MOBMOD   = 1              NQSMOD   = 0              NOIMOD   = 1
+CAPMOD   = 3              XPART    = 0.5            CGSO     = 6.00E-11
+CGDO     = 1.00E-10       CGBO     = 0              CGSL     = 0
+CGDL     = 6.00E-09       CKAPPA   = 1.20           CF       = 0
+CLC      = 3.0E-09        CLE      = 0.8            DWC      = 0
+DLC      = -1.00E-06      NOFF     = 3.66           VOFFCV   = -0.40
+ACDE     = 1.0            MOIN     = 15             CJ       = 2.00E-03
+MJ       = 0.35           PB       = 0.65           JS       = 1.00E-03
+NJ       = 1.30           XTI      = 3.0            IJTH     = 0
+KT1      = -0.6           UTE      = -0.6           PRT      = 3.00E06
+AT       = 3.3E04         )


In Ltspice I used an .include statement for the xxx.txt file, added an nmos symbol with VALUE = 2SK4177. When I run the simulation, the model is accepted but the MOSFET current is just 50uA (not 100mA as expected and proven by a different MOSFET from the standard Ltspice library).

What is wrong? I wonder if the level 8 model works in Ltspice. If not, how can I change the model to make it work? I haven't found any other model for 2SK4177.

When you deleted that "everything" else you also deleted the information about the width, length, and area (and some others):

* Temp = 27 deg
* W    =   228740 E-6 m
* L    =      3.0 E-6 m
* AD   =   228740 E-12 m2
* RG   =        9 ohm
* RB   =    0.045 ohm


If you'll CtrlRClick on the symbol and add in one of the Value2, SpiceLine, or SpiceLine2 this line:

w=228.74m l=3u ad=228.74n


you'll see that the drain current is ~90 mA. Don't forget that, when you picked a model from the database (I'm guessing STW11NM80, the highest Vds), those transistors are VDMOS, a bit different than the NMOS/PMOS, which are meant to be monolithic MOSFETs. BTW, don't forget that the VDMOS has a builtin antiparallel diode, the NMOS doesn't. Well, you could say "technically", but, really...

• @Hyp I would use an nmos4 symbol and add those two resistors as discrete components (as shown in the PDF). Level=8 (or BSIM3) models don't have RB and RG parameters. Speaking of which, it's bizarre they supply a BSIM3 model for a power MOSFET. They're usually supplied as subcircuits to properly model the gate-drain capacitance and gate charge of the vertical topology. You could screw around with making your own VDMOS model but I don't know if it's worth it. I suggest try what they supplied and see how far it gets you first. Jul 14 at 16:41
• @SteKulov That's what puzzled me, too: I thought the .model was part of a composite .subckt, but there's not even a hint of a body diode (which is shown in the datasheet). Jul 14 at 18:29
• The monolithic MOS models in SPICE do have PN junctions as shown by Fig 4-6 and Eq 4-31 & 4-32. I believe the same holds for BSIM3 and the parameters for the junctions in that case are JS, NJ, and IJTH. The external RB is for adding diode ohmic resistance. See Chapter 9 of the BSIM3 manual for more details on that. Jul 14 at 19:41
• @SteKulov I seem to remember Mike saying that they're modelled and connected slightly different than an anti-parallel diode, as shown in the LTspice manual (LTspice > Circuit Elements > M. ..), even if connecting the substrate to the source would achieve the same thing. That's why I said "technically". Something about an actual diode model used in there, that's why it borrows the Is, Cjo, ..` parameters. But don't quote me, I'm not sure about this. Jul 14 at 21:12
• Yah, that's all true. I guess I shouldn't compare apples and oranges. The Level 1/2/3 models are the only ones that the textbook Figure is valid for, and it's different than a VDMOS which has the body diode path going around both Rd and Rs (instead of just Rs). BSIM3 model has no explicit Rd and Rs and uses a per area sheet resistance Rsh, so I don't know exactly what the deal is. Most subcircuit power MOSFET models I come across use a LEVEL=3 and an explicit body diode overriding the built-in one. Anyway, my point is that I'm more skeptical of the gate charge stuff than the diode. Jul 15 at 5:07