# How does this phase advance loop filter work?

I am reading this paper titled A Versatile Digital GHz Phase Lock for External Cavity Diode Lasers. This is part of the circuit.

I am confused about the functionality of the part labeled "Phase Advance Filter."

The paper says:

two mechanisms oppose each other, which leads to a phase shift of 180◦ at modulation frequencies typically between 1 and 10 MHz [7]. In order to partly compensate for this effect, a phase-advance loop filter is used in the fast feedback path, followed by a buffer stage (IC1D) with an adjustable gain to drive the laser diode current modulator.

The two mechanisms being at low frequencies the lasing medium temperature changes so the lasing medium's refractive index changes, and at high frequencies there are current-induced charge densities which affect the refractive index of the medium.

How does this filter (at least partly) oppose these mechanisms?

When I tried to solve the transfer function for the phase advance loop filter, I find this as a Bode Plot. I don't think this is right however, because it says the phase angle doesn't change in frequency when it should since frequencies between 1MHz and 10Mhz should be 180 degrees out of phase. Can someone help me to derive the transfer function?

• Without doing too much analysis, it looks like it provides a zero and pole for a phase boost in the desired region. Jul 14, 2022 at 17:06
• Can you elaborate on that? How does it form a pole and a 0? And to figure out the desired frequency range, would you have to derive the transfer function? Jul 14, 2022 at 18:26
• You basically have an impedance divider formed by C12, R29, R21 and R23. At DC, the cap is open. As frequency increases, the impedance of the cap decreases causing the transfer function to increase- the zero. As the cap impedance gets smaller compared to R29 the increase flattens off- the pole. The transfer function would be easy to derive and you can then use a Bode plot to see the response. Jul 14, 2022 at 19:39

Without C12, R29 and R21 form a voltage divider with flat phase.

With C1, you get a phase advance to AC waveforms. The effect of this would be more clearly shown by drawing the Bode plot for the whole feedback loop. It reduces the increase of phase of the rest of the loop at frequencies around the R29/C12 frequency, making stability easier to achieve, or even possible.

• How could you plot the bode diagram for this loop? Would it involve having to find the transfer function for this loop? Jul 14, 2022 at 18:28
• @LennonKirby Yes. Jul 14, 2022 at 18:40
• would this be the correct transfer function for R29, C12, and R21 T(s) = R21(1+C12*R29*s)/[R21(1+C12*R29*S)+R19]? Jul 14, 2022 at 21:58

This is a dual Laser mode hopping OPLL or optical phase-locked loop.

The wording "phase advance filter "makes it more interesting but is not unique to PLL's and the correct number of inversions for each modulator are needed to make negative feedback.

details

There are two modulations frequency sources from DC to RF and DC to LF which have inverse effects on the laser temperature and thus refraction index with the direction of control chosen and that controls the wavelength of the laser using electro-optical (EO) and acoustic-optical (AO) modulation.

There must be negative feedback from both to be stable within their respective current and phase/frequency ranges. The result is achieved by the correct number of inverting amplifiers and phase lead/lag compensation, which is common in most PLL's.

The unique part of this design is the dual EO AO locked lasers using a common low frequency (<1MHz) reference with microwave bandwidths. But their abstract is a little more interesting "The locking range thus covers ground-state hyperfine splittings of all alkali metals"

The error voltage requires conditioning for OPLL control with proportional integrator LPF to provide DC and low jitter from ripple. Most PLL's use lead-lag compensation for improved stability. That phase-lead compensation is partial differentiation or an HPF with partial DC gain and now you have a dual mode-locked PID control system.