I was thinking about transistor design, and how the classic AND gate is composed of two transistors in series. See this image:

enter image description here

Now if we look at how a transistor itself is designed we can expand the transistor (NPN MOSFET for example) with the following schematic:

MOSFET layout source

So effectively our "AND gate" at the chemical level looks something like this:

enter image description here

Now this seems wasteful to me, since we could have easily done away the 2nd and 3rd N-type regions and instead just done:

Image of AND gate with 3 N type regions and 2 gates

Which would reduce the number of N type regions required by nearly 33%.

So I guess in a short version, why do we not do this type sub-transistor-level optimization when building circuits?

Moreover, this can be generalized beyond gates, for example, you can natively re-implement any circuit at this level of abstraction allowing you to (at the doped chemical level) get an adder or a multiplier etc. and then only have wires between these large atomic units.

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    \$\begingroup\$ In the first picture you show us BJTs while the rest of the pictures are MOSFETs.Also in the first picture that circuit isnt a AND gate. \$\endgroup\$
    – Miss Mulan
    Jul 15, 2022 at 0:50
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    \$\begingroup\$ Have you ever seen a VLSI layout? The actual gates are not usually built using discrete transistors. \$\endgroup\$
    – Eugene Sh.
    Jul 15, 2022 at 0:51
  • \$\begingroup\$ @EugeneSh. I have not seen one, I admit im a layman but is there a place you'd recommend to look first? Perhaps everything i'm saying here is trivial/already considered. \$\endgroup\$ Jul 15, 2022 at 0:52
  • \$\begingroup\$ @MissMulan im sorry, i thought that was an AND gate diagram, i guess it was the first thing that came up on google and matched what i thought was a source wire at the top, two inputs on the left and an output at the bottom. Let me find a correct image, although a lot of them seem to have even more transistors \$\endgroup\$ Jul 15, 2022 at 0:55
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    \$\begingroup\$ The basic TTL NAND uses multi-emitter transistors, one emitter for each input. You can buy dual-gate FETs, which could implement the AND gates you show, although they are typically used for gain-controlled and high freqency amplifiers. \$\endgroup\$
    – Neil_UK
    Jul 15, 2022 at 5:47

2 Answers 2


So I guess in a short version, why do we not do this type sub transistor level optimization when building circuits?

Your mistake is looking into introductory sources, where everything is simplified. Nobody designs AND gates out of two transistors, and nobody lays out ICs as if they were discrete MOSFETs. The picture of a mosfet you show is only accurate when the mosfet is alone. In an IC, lots of tricks are possible.

What you show as effectively our "AND gate" at the chemical level looks something like is not how it's done, and the "optimization" you show is a common layout technique, and is taken even further. Remember that ICs are 3D, not 2D, and typically the transistors on the layout aren't circular. So the cross-section you show is quite limiting and leaves a lot of the detail out.

For a good hands-on introduction to making ICs, see Sam Zeloof's experimental results.


It is done the way you draw. Most logic circuits are CMOS (contain NMOS and PMOS devices; no DC current). In general this means there are usually strings of 2 or more series connected devices, and they are connected exactly as you show -- there is no exposed drain1-to-source2 connection. This not only saves space, but also reduces parasitic capacitance which improves speed and saves power.

However there are usually equal numbers of parallel-connected devices and they cannot share connections exactly this way.


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