I'm trying to dig into the early IBM PC's arhictecture, and got stuck with one thing that is not really clear to me. Every PC XT schematic I saw, including the original one from "IBM 5160 Technical Reference" use AMW and AIOW (sometimes also referred as AMWC and AIOWC) active low signals of the 8288 bus controller as their memory/IO write strobes. For example, this schematic:
As you can see, normal write (MWT and IOW) signals are left unconnected here. And, as far as I understand, target memory/IO device uses AMW/AIOW signal, or, to be more precise its leading edge (high-to-low) transition as a command to read the data from the data bus. However 8088/8086 datasheets say this:
The 82C88 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write.
This sounds confusing, because this means that any device that uses advanced write strobes of the 8288 bus controller is going to read garbase, because CPU has not yet provided any meaningful data to the bus. So, I am wondering how it still works that way in the IBM PC XT, and where I am wrong in my conclusions?
What is the purpose of these advanced write signals, and why PC XT designers used them instead of normal write strobes, which would have data perfectly valid at their leading edge?
UPDATE: At first I accepted @Kuba hasn't forgotten Monica's answer, but then went to check the schematics again, and it seems that target devices actually use leading (high-to-low) transition to read the data from the bus. Like 8253A PIT does here:
IOW is connected to the WR input of 8253A, its WR input is active low, and 8253A datasheet says:
So, my above questions still remain relevant. Isn't 8253A going to read anything but the real data in this case? Because at this point, when advanced write strobe goes low, CPU is not actually outputting data on the bus.