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Consider this scenario: A microcontroller/microprocessor IC's input/output(GPIO) pins are connected to some other IC onboard, say IC 'X'. Now X has some big decoupling capacitors. Now there is a power loss event or simply the system is turned off. The decoupling capacitors on X hold enough charge to power X long after the microcontroller/microprocessor has lost all of its power. Now the X is still powering the input/output pins of the microcontroller/microprocessor for a few milliseconds.

Will this scenario cause damage the to microcontroller/microprocessor?

The microcontroller/microprocessor in my case is "Texas Instruments AM6442" I had read somewhere that it is NOT allowed to power input/output pins with the AM6442 turned off. Unfortunatley I am not able to relocate where I read this but the Internet says so this is true in general for all microcontrollers/microprocessors.

AM6442 datahseet: https://www.ti.com/lit/ds/symlink/am6442.pdf?ts=1658082725697&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FAM6442

If yes damage can be caused, what might be the possible solutions be to this problem.

Thanks

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    \$\begingroup\$ Yes, it can. There are several other issues to such a configuration as well. This sounds like a hack at best, and a situation greatly in need of a load switch type device. \$\endgroup\$ Commented Jul 17, 2022 at 18:10
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    \$\begingroup\$ Most likely this does not answer the question you really have, but yes, GPIO pins don't like that, and the easy solution is to not power other chips and decoupling capacitors via a GPIO pin. Some MCUs can tolerate a voltage on GPIO pin while unpowered, but you can check MCU datasheet about that. \$\endgroup\$
    – Justme
    Commented Jul 17, 2022 at 18:23
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    \$\begingroup\$ @AbhimanyuSIngh I think the potential for damage would then depend on the output impedance of chip X that's connected to the GPIO of the microcontroller. High impedance sources are going to be fine in my opinion. \$\endgroup\$
    – Bryan
    Commented Jul 17, 2022 at 18:35
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    \$\begingroup\$ Well, check the datasheet first; some chips don't care about startup order. Others are very picky, and you will have to push back on who/whatever is handling power supplies, or use additional power domains, or bus interfaces to avoid backfeeding GPIOs, etc. Basically, keep reading the datasheet. \$\endgroup\$ Commented Jul 17, 2022 at 19:44
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    \$\begingroup\$ See note (4) of the Absolute Maximum Ratings, page 99 of the datasheet. The manufacturer suggests that what you plan to do is not allowed. If you want a reliable system your only choice is to comply with the datasheet. \$\endgroup\$ Commented Jul 17, 2022 at 20:24

3 Answers 3

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In general all microprocessors and most other IC's have potential to be damaged if the IO pins are held high when the processor IO supply is not powered up. The trick is to make sure that doesn't happen. Sometimes it can be done with sequencing, other times you may need little transistor circuits.

Other times you can interpose a special buffer to isolate the IC with de-powered IO from the power source. In particular, buffers which advertise the "Ioff" property are designed so that when VDD is not present, all inputs and outputs maintain high impedance and isolation.

Ioff Buffers

The images and accompanying text are from TI's website, but TI is not the only vendor to make isolation switches like these.

Image Source

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What you're describing is a typical power sequencing issue that designers face all the time, although yours is a transient problem rather than a DC one.

Here's the general scenario. You have two assemblies A & B, with A driving B. Assembly A is powered by power supply (PS) A, and assembly B is powered by PS B. Assembly A powers up before assembly B and thus could drive assembly B's inputs before its devices are powered up. This is usually not desired, as it could forward bias the ESD protection diodes on the inputs of ICs.

In such a scenario, we would add resistors in series with those interfaces, so that the current that flows through those ESD diodes is limited. The value of those resistors depends on the particulars of the input characteristic of the destination device.

Note that differential interfaces usually don't have a problem with this scenario.

We ran into this doing a deep dive into one of our designs. We had an 3.3V IO powered FPGA driving some signals into a 5V powered FCT245. It was discovered that the 5V supply could (not always) come up after the 3.3V supply. So we added the aforementioned series resistors to those signals.

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  • \$\begingroup\$ Interesting Solution. I actually don't understand what actually is there to be damage inside the microcontroller being back powered by GPIO pins. So after your answer I assume the ESD diodes are at risk mainly? This soltuion of using series resistor seems to good to be true. Have you used it before often? Has it ever failed on you. If this works this would be the most simplest yet the most elegant solution to this problem. I think i might use it \$\endgroup\$
    – Bubu
    Commented Jul 22, 2022 at 11:33
  • \$\begingroup\$ Yes, we've used that technique. It works in the sense that parts haven't been damaged during power cycling. But then again, they may not have been damaged even without the resistors. This is about being able to quantify, and limit the maximum current that the ESD diodes and their associated interconnects would have to carry, in order to ameliorate electro-migration concerns. This was done for an application with a 15-20 year life time. \$\endgroup\$
    – SteveSh
    Commented Jul 22, 2022 at 12:33
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Yes, this can damage the microcontroller. Whether is actually does, depends on several factors:

1.) the microcontroller probably has some protection diodes from the GPIO pins to the power supply rails. These diodes are not particularly strong though, check the MCU's datasheet to find out what can be tolerated.

2.) obviously the problem only arises if the connection to chip X leads to an output pin of X. Output pins only have a limited output impedance, i.e. can only source a limited amount of current. X's datasheet will tell you how much, and you can compare this figure to the one checked under point (1).

3.) you're talking about 'big decoupling' capacitance, whatever that means. 100µF is a big decoupling capacitor for most ICs, but it cannot sustain the current long enough to damage the MCU. But if you're talking about thousands or even ten-thousends of µF, the potential is there.

You're safe if the number determined from (1) is larger than the one from (2). If not, and the capacitance is really large as in (3), then there are two simple solutions. Both involve using diodes (for reduced drop use Schottkys). In one solution, you just strengthen the protection diodes by connecting external diodes in parallel (anode to the GPIO pin, cathode to the MCU's positive power rail). This may be cumbersome if there are several connections from the MCU to X. In that case I'd suggest to connect one diode, with the anode to X's positive power rail, and the cathode to the MCU's positive power rail. In both cases, you're effectively ensuring that the MCU's power rail potential is never more than 0.3V under the GPIO pin's potential, which is safe for the MCU.

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  • \$\begingroup\$ Adding external protection diodes seems to be a safe and practical solution. Also, in general, GPIO inputs should always be connected to sources with a current limiting resistor of some sort. Another helpful practice is to connect diodes from output to input of voltage regulators, so large decoupling capacitors will discharge into the raw voltage supply to avoid reverse biasing regulators or "starving" the inputs. \$\endgroup\$
    – PStechPaul
    Commented Jul 21, 2022 at 23:03
  • \$\begingroup\$ This is a very interesting. Both of solutions in the scenarios 1<2 are genius. Unfortunatley TI's datasheet are nothing less than garbage. They assume they are making for themselves. So calculating if 1<2 is not luxury for my case. But still this is very insightful. Also the 2 solutions you provide should work pretty great ONLY IF you could backpower MCU's power rail with MCU pins/X's power rail. Assume the scenario where the X is powered using 3.3V or 1.8V and the MCU is powered by extra 5V. X's power rail wouldnt be able backfeed all MCU's power rails. \$\endgroup\$
    – Bubu
    Commented Jul 22, 2022 at 11:51
  • \$\begingroup\$ What you describe is not a problem. If X is powered by any voltage less than the MCU's voltage, then during normal operation the diode is reverse biased, so no current flows. At power failure, during the supply voltage ramp-down, the MCU is not in danger anyway while the ramping voltage is still larger than X's voltage. Only when the voltage get's lower than X's supply, the diode starts conducting, powering the MCU from X's bypass capacitors, until they're discharged. \$\endgroup\$ Commented Jul 22, 2022 at 18:29

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