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In the logic symbol below, in order to create an 8-bit counter, how should I make the connections so that each 74293 chip (4-bit counter) can turn into an 8-bit counter?

I know that in an asynchronous counter, the output of the first counter must be connected to the clock of the second counter. But in this case, I have two clock pins and 4 outputs (Q3, Q2, Q1, Q0). Is there any approach to transform it?

74293 iC

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    \$\begingroup\$ just connect them and see what happens \$\endgroup\$
    – jsotola
    Jul 18 at 5:16
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    \$\begingroup\$ 74293 is not a 4-bit counter, it's a 3-bit plus a 1-bit, independent save for the reset inputs and power. \$\endgroup\$ Jul 18 at 5:53

2 Answers 2

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As with every IC, you should find out as much as you can about what's inside it and how it works to get the best from it. Such info' comes from datasheets, application notes, white papers, example designs etc.

Here, the Texas Instruments 74293 datasheet shows the below internal circuit. It shows two clocked counters made from 4 JKFFs: a 1-bit counter and a 3-bit ripple counter. The four JKFFs share an asynchronous reset, active when R0(1) and R0(2) are both asserted.

enter image description here

The question wants to make a single 8-bit ripple counter from two 74293 ICs, which is straightforward. Using 74293 ICs U1 and U2, the connections are:

  clock  -->  U1.INPUTA
  U1.QA  -->  U1.INPUTB

  U1.QD  -->  U2.INPUTA
  U2.QA  -->  U2.INPUTB

The 8-bit counter output is then, from MSB to LSB:

  U2.QD, U2.QC, U2.QB, U2.QA, U1.QD, U1.QC, U1.QB, U1.QA 

For the asynchronous resets, you can connect both R0(2) pins HIGH and both R0(1) together as a single counter reset signal, the active-HIGH RST_CTR.

RST_CTR can be driven by an existing signal in your design, such as a counter clear or power-on reset. If you don't have the latter, one by produced by a simple RC with a strong diode to protect RST_CTR (and its weak internal diode) by discharging the capacitor on power-down. An example is shown below.

schematic

simulate this circuit – Schematic created using CircuitLab

The RC values must make the RST_CTR rise time lag the supply rail's rise time, while keeping the rise time as fast as possible. It must ensure that RST_CTR is held at a valid logic HIGH for (e.g.) 1 us after the supply rail has reached the 74293 min. operating voltage. Purely example values are shown. Calculate your correct values using the datasheet.

Ideally, the counter clock should not have a rising edge as RST_CTR goes from asserted to negated. Otherwise, some counter JKFFs may go metastable. They will recover to valid levels before the next clock edge unless the clock frequency is above a maximum. Again, that's a datasheet analysis exercise.

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The datasheet shows how the flip-flops are connected:

SN74LS293 logic diagram

This device actually has a one-bit and a three-bit counter, and the datasheet tells you how to combine them:

To use the maximum count length (four-bit binary) of these counters, the B input is connected to the QA output.

Please note that this kind of connection is also how the three-bit counter is implemented.

The counters in multiple chips can be combined in the same way.

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