I have been working for quite some time now with Xilinx ISE 14.7 on Debian development machines. Before the suggestion comes: We use a Virtex-6 FPGA for our research and have no option to switch to something Vivado compatible (besides, they are perfectly good and adequate chips).
We have an elaborate design conducting real-time processing of experimental data using various Coregen IP cores although most of the design is hand-written VHDL. We run Xilinx on a Debian machine. I have used Debian(-based) systems for most of my development career and so far no problems have arisen that I could not fix. To build, we mostly use a Makefile based workflow, but the problem I describe is valid for the GUI build chain as well, as the same error is thrown.
The Problem: When coregen cores (in particular chipscope cores, but also FIR filter cores) are being generated the coreutil seems to failed with some weird Java error:
$ source /opt/Xilinx/14.7/ISE_DS/settings64.sh && coregen -b csVIO.xco -p coregen.cgc
. /opt/Xilinx/14.7/ISE_DS/common/.settings64.sh /opt/Xilinx/14.7/ISE_DS/common
. /opt/Xilinx/14.7/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.7/ISE_DS/EDK
. /opt/Xilinx/14.7/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.7/ISE_DS/PlanAhead
. /opt/Xilinx/14.7/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.7/ISE_DS/ISE
Release 14.7 - Xilinx CORE Generator P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in /hostshare/src/coregen/coregen.log
INFO:encore:314 - Created non-GUI application for batch mode execution.
INFO:sim:172 - Generating IP...
Resolving generic values...
Finished resolving generic values.
Generating IP...
WARNING:sim:89 - A core named <csVIO> already exists in the output directory.
Output products for this core may be overwritten.
Configuring files for csVIO root...
WARNING:coreutil - Failed to generate file: chipscope_bb_lib
invoked from within
"deliverEJava [getComponentName] {}"
(procedure "components::csVIO::pre_generation" line 53)
invoked from within
"$PreGenerationTargets"
(procedure "::xilinx::sim::generation::generatePsfCore" line 55)
invoked from within
"::xilinx::sim::generation::generatePsfCore {chipscope_vio_v1_05_a} {csVIO}
{ALL}"ERROR:sim - Failed to generate file: chipscope_bb_lib
ERROR:sim - Error found during generation.
ERROR:sim - Failed to generate 'csVIO'. Failed to generate file:
chipscope_bb_lib
ERROR:sim:877 - Error found during execution of IP 'VIO (ChipScope Pro - Virtual
Input/Output) v1.05.a'
make: *** [Makefile:51: csVIO.vhd] Error 1
Now the weird thing about this is, that this error only occurs in Debian distributions from 10 ("buster") and up. I have done elaborate VM-based testing and the problem does NOT occur on Debian 9 ("stretch") and down.
I have another seemingly similar error during the mapping stage, for which I don't have an example right now.
The question to the community is, whether anyone has also found this error and managed to fix this or can explain to me, what changed from Debian 9 to 10, that made this error appear? The only thing I can remotely identify from the Debian changelog, is that AppArmor is enabled by default. Could this be the cause (I just realize this as I write this)?
If so, how do I fix this?
Thanks in advance for any helpful suggestions. I could not find this problem answered anywhere, but if you have a source for a solution, please point me in the direction and accept my humble apology.
