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I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches.

Verilog input wire has been declared in the simple memory read write which connects to these DIP switches on an external breakout. The program is currently not working in this setup.

My question is if giving external DIP switch for WEN and REN signals is a good idea?

enter image description here

Some more details:

FPGA device is ProASIC3 A3P250.

Board is custom made eval board where all FPGA's 208 pins are coming to a jumper.

DIP switch is switched by hand.

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    \$\begingroup\$ Hopefully your FPGA design debounces the switch inputs. If it doesn't then I'd suggest you add it. \$\endgroup\$
    – Kartman
    Jul 20, 2022 at 12:37
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    \$\begingroup\$ If external switches, not part of the development board, you may want to debounce it either in RTL or using external ckt. \$\endgroup\$
    – Mitu Raj
    Jul 20, 2022 at 13:34

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