# Limit of daisy-chaining of multiple ADCs

I am designing a device consisting of 20 daisy-chained ADCs (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7685.pdf) communicating via SPI with the STM32F303 microprocessor. I have a question regarding the sampling rate per channel. If the Nyquist frequency is 20kHz, is it possible to achieve an adequate (> 40kSPS) sampling rate for each channel having 20 chips? Is there some kind of equation that expresses the relationship between sampling rate and the number of devices in a daisy chain? And finally, should I consider some other limiters apart from the number of chips in the daisy chain, reading time for example?

• Note that if you want 20 kHz analog bandwidth, sampling at 40 kSPS leaves very little room for anti-alias filtering.
– jpa
Commented Jul 21, 2022 at 18:32

This should be perfectly feasible.

The AD7685 is designed for this, and has an integrated sampling clock, meaning that the only limiting factor for you is the SPI clock rate. You need to allow for enough time to clock 20×16 bits out 40000 times per second, and allow for some minor extra processing time in between reads.

20×16×40000 = 12.8 MHz which requires an SPI clock period of 78 ns. This is well above the minimum listed in the datasheet:

SCK Period (Chain Mode) Min Unit
VIO Above 4.5V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns
VIO Above 2.3 V 20 ns
• And what about the clock speed of MCU? STM32F303's maximum SPI clock frequency is 24MHz (I am referring to st.com/resource/en/datasheet/stm32f303vc.pdf page 97), which seems to agree with my conditions. So if I take a sampling rate of 75kSPS for less aliasing purposes, then it should be also fine. Am I right? Commented Jul 21, 2022 at 6:34
• @Valeriya Sure, but make sure you can use DMA for this, so the time taken to shuffle the bits around doesn't completely swamp everything else you might want to do with the data.
– pipe
Commented Jul 21, 2022 at 7:23

That sounds extremely expensive; is there a reason to choose a single-channel ADC? There seem to be many options with multiple inputs (muxed or simultaneous sampling), in the same price even.

As for the AD7685, max clock is over 50MHz (50Mbps data rate), so it would seem, assuming you can feed the SPI channel at that rate (STM32F3, that's going to have a DMA to handle it, right?), 40kSps * 16b/Sp = 320kbps/ch; 50Mbps / 0.32Mbps ~= 156 channels.

It's just ratios of data rates.

You'll run out of trace length long before then, I'm pretty sure. Mind the clock skew, let alone signal quality and EMI, on such a lengthy bus.

With octal ADCs, you only need three of them, a trivial arrangement as far as the SPI bus is concerned.

• You try and find a device comparable with the AD7685 that has two channels or more. Commented Jul 21, 2022 at 8:19
• @Andyaka Could you be more specific? At a glance, I see a 250kSps, 16b true differential ADC. There are numerous results that match such a description. Commented Jul 21, 2022 at 18:35
• INL, DNL, distortion, low offset and gain errors; when I used it (many used together in a proper design) it was the best ADC available for measurements. Of course, better ones may have surfaced since 2017 but they won't beat it by much. It's pseudo differential BTW from memory. Commented Jul 21, 2022 at 18:38