Self-biased JFET common-source amplifier

I am trying to design a simple common source jfet amplifier using a J109 transistor. I'm using the J109 datasheet and equations from the book Electronic Devices by Thomas L. Floyd. The issue is that I do not obtain the right values of resistors to achieve maximum voltage gain.

Parameters :

Vdd = 12V Id = 0.5Idss = 0.02 A Vgs ≈ Vp/3.4 ≈ -1.75 V Vd = 0.5Vdd =6V

Components values :

Rs = |Vgs/Id| = 1.75/0.02 ≈ 88Ω

Rd = (Vdd-Vd)/Id = (12-6)/0.02 = 300Ω

I arbitrarely choosed 100µF for the bypass capacitor since I don't really care about the cutoff frequency in this case.

I built the circuit on a breadboard and it worked except the gain was only about 1.67 (unloaded coutput), which I found quite low. (I fed a 1KHz sine wave from a function generator to the input and measured the output with a scope).

I was using potentiometers for Rs and Rd and after adjusting those, I managed to get a gain of ten with values of Rs = 265Ω and Rd = 390Ω.

I just don't understand why I get such a small gain using the results from the equations. What is wrong with my calculations ?

  • 3
    \$\begingroup\$ Depletion-mode JFETs have notoriously broad specifications. For example, IDSS is shown as 40mA minimum, with open-end maximum. Similarly, pinch-off voltage covers a broad range from -2 to -6 V. As you have done, users often hunt for best bias. Perhaps this is why you don't see these JFETs used often as amplifiers - when a designer does use them, he/she might specify binned parts. \$\endgroup\$
    – glen_geek
    Jul 22 at 13:08


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